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VERSION:2.0
PRODID:-//Memento EPFL//
BEGIN:VEVENT
SUMMARY:RISC-V: Instruction sets want to be free
DTSTART:20170522T103000
DTEND:20170522T114500
DTSTAMP:20260920T132640Z
UID:347fab9e3a81cb6e049e7262659a90ba682fab28d777409a11e1fbb9
CATEGORIES:Conferences - Seminars
DESCRIPTION:Krste Asanović\, Professor in the EECS Department at the Univ
 ersity of California\, Berkeley\nThe most important interface in a compute
 r system is the instruction set architecture (ISA) as it connects software
  to hardware.  So\, given the prevalence of open standards for almost all
  other important interfaces\, why is the ISA still proprietary?  We argue
  that a free ISA is a necessary precursor to future hardware innovation\, 
 and there's no good technical reason not to have free\, open ISAs just as 
 we have free\, open networking standards and free\, open operating systems
 .\n\nThe free and open RISC-V ISA began development at UC Berkeley in 2010
 \, with the frozen base user ISA standard released in May 2014\, and has s
 ince seen rapid uptake around the globe\, including the first commercial s
 hipments.  This talk will cover the technical features of the RISC-V ISA 
 design\, which has the goals of scaling from the tiniest implementations f
 or IoT up to the largest warehouse-scale computers\, with support for exte
 nsive customization.  We'll also describe three different industry-compet
 itive open-source cores developed at UC Berkeley\, all written in Chisel\,
  a productive new open-source hardware\ndesign language.  Finally\, we'll
  describe the uptake of RISC-V and the development of the RISC-V ecosystem
 \, including the RISC-V Foundation.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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