BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Memento EPFL// BEGIN:VEVENT SUMMARY:Artificial Intelligence (AI): Myths\, Realities\, and Challenges DTSTART:20170630T110000 DTEND:20170630T120000 DTSTAMP:20260511T072949Z UID:47621daaf53010e0b1c15f3f12488ed86de99dc093c515ad52361d5e CATEGORIES:Conferences - Seminars DESCRIPTION:Victor Grimblatt\, Synopsys Chile R&D Center\nLast year\, in S eoul\, a computer program called AlphaGo defeated 9 dan ranking\, and 18 t imes Go world champion Lee Sedol by a score of 4-1. This year\, in Barcelo na\, SoftBank Founder & CEO\, Masayashi Son\, in his MWC17 keynote predict ed that by 2045 computers made with chips integrating 3 quadrillion transi stors\, will have a 10\,000 IQ. Artificial intelligence is changing the ru les of the game: new computing architectures are emerging that lead to new classes of processors in the cloud\, as well as in the "things" aimed at revolutionizing our life: robotics\, cars\, homes\, phones\, "every thing" gets smarter. It is hard to overstate the promises and the challenges we are facing in the new applications emerging in the age of smarter "every t hing".\n\nMoore's law continues\, quasi-relentlessly to enable exponential ly larger chips manufactured using Angstrom-level process technologies\, t hus requiring smarter IC design tools\; artificial intelligence may have a n impact also on EDA\, where the sheer complexity\, which is approaching t he limits of "plain" computation\, could be addressed by "teaching" a "bra in" how to solve certain classes of problems. Beyond Moore\, better\, tigh ter\, smarter "integration" of processors and memory\, delivering much hig her bandwidth\, enables new classes of processors - such as TPU - exponent ially more parallel in architecture\, thus enabling faster "machine learni ng". On the one hand\, AI may help EDA leapfrog the sheer complexity of An gstrom-level process technologies\; on the other hand\, innovative EDA may help AI happen.\n\nOur entire industry is under pressure to de-risk and s peed-up the critical intersections. Smartness is "every thing" !\n\nBio:\n Victor Grimblatt has an engineering diploma in microelectronics from Insti tut Nationale Polytechnique de Grenoble (INPG - France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile).   He is currently R&D Group Director and General Manager of Synopsys Chil e\, leader in Electronic Design Automation (EDA). He opened the Synopsys C hile R&D Center in 2006. He has expertise and knowledge in business and te chnology and understands very well the trends of the electronic industry\; therefore\, he is often consulted for new technological business developm ent.\nBefore joining Synopsys\, he worked for different Chilean and multin ational companies\, such as Motorola Semiconductors\, Honeywell Bull\, VLS I technology Inc.\, and Compass Design Automation Inc. He started to work in EDA in 1988 in VLSI Technology Inc. where he developed synthesis tools being one of the pioneers of this new technology. He also worked in embedd ed systems development in Motorola semiconductors.\n\nIn 1990 he was invit ed by professor McCluskey to present his work in Logic Synthesis at the CR C - Stanford University.  He has published several papers in EDA and embe dded systems development\, and since 2007 he has been invited to several L atin American Conferences (Argentina\, Brazil\, Chile\, Mexico\, Peru and Uruguay) to talk about Circuit Design\, EDA\, and Embedded Systems. From 2 006 to 2008 he was member of the "Chilean Offshoring Committee" organized by the Minister of Economy of Chile.  In 2010 he was awarded as "Innovato r of the Year in Services Export". In 2012 he was nominated to best engine er of Chile. In 2016 he was awarded as "Member of the Year" by Bristol Who 's Who. He is also member of several Technical Program Committees on Circu it Design and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. Since 2016 he is President of the Chilean Electronic s and Electrical Industry Association. LOCATION:INF 328 http://plan.epfl.ch/?room=INF328 STATUS:CONFIRMED END:VEVENT END:VCALENDAR