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SUMMARY:System Seminars - Title : Directed Speculation in Multicore Memory
  Systems to Improve Performance and Efficiency
DTSTART:20120511T133000
DTEND:20120511T150000
DTSTAMP:20260407T175719Z
UID:83735aae3eec13ced1e73941ee81925f0d5cfcbb1d0a226f3ecf0675
CATEGORIES:Conferences - Seminars
DESCRIPTION:Dr. Paul V. Gratz\, Department of ECE Texas A&M University\nAb
 stract :\nThe scaling of multi-core processors poses a challenge to memory
  system design.  While process technology scaling provides greater number
 s of cores on each chip\, the transistor performance and power gains that 
 traditionally accompanied process scaling have largely ceased.  Scaling p
 erformance with increased core counts must be achieved under the same or r
 educed energy and power budgets.\nFurthermore\, increased cores generate m
 ore accesses to shared caches causing conflict misses as unrelated process
 es compete for the same cache sets.  Each miss represents significant was
 te: wasted time as the requested data is transferred from a slow main memo
 ry\, wasted energy and bandwidth when transferring cache block words that 
 will ultimately go unused.  In this talk I will explore the means to leve
 rage memory locality speculation to reduce waste and improve efficiency in
  multi-core processor memory systems.  In particular\, I will show how co
 ntrol flow and effective address speculation can be used in a novel prefet
 ch engine that improves IPC by 39%\, outperforming the best competing desi
 gn with 3X the hardware state overhead. I will also demonstrate a techniqu
 e to speculate on word usage within processor cache lines to eliminate 36%
  of the dynamic energy in the multi-core processor interconnect with no pe
 rformance impact.\n\nBio :\nPaul V. Gratz is an Assistant Professor in the
  department of Electrical and Computer Engineering at Texas A&M University
 .  His research interests include energy efficient and reliable design in
  the context of high performance computer architecture\, processor memory 
 systems and on-chip interconnection networks.  He received his B.S. and M
 .S. degrees in Electrical Engineering from The University of Florida in 19
 94 and 1997 respectively.  From 1997 to 2002 he was a design engineer wit
 h Intel Corporation.  He received his Ph.D. degree in Electrical and Comp
 uter Engineering from the University of Texas at Austin in 2008.  His pap
 er "B-Fetch:Branch Prediction Directed Prefetching for In-Order Processors
 " was selected as one of four "Best Papers from IEEE Computer Architecture
  Letters in 2011".  At ASPLOS '09\, Dr. Gratz co-authored "An Evaluation 
 of the TRIPS Computer System\," receiving a best paper award.  In Spring 
 2010\, he received the "Teaching Excellence Award - Top 5%" award from the
  Texas A&M University System for a graduate-level Advanced Computer Archit
 ecture course he developed.
LOCATION:BC 410 https://plan.epfl.ch/?room==BC%20410
STATUS:CONFIRMED
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