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SUMMARY:The Hardware Acceleration Renaissance
DTSTART:20180711T100000
DTEND:20180711T120000
DTSTAMP:20260408T060322Z
UID:a25d47ae644d0e8017fe166c99bbb720d6a342b0ae9e1195cf6de9b1
CATEGORIES:Conferences - Seminars
DESCRIPTION:Sahand Kashani-Akhavan\nEDIC candidacy exam\nExam president: P
 rof. Paolo Ienne\nThesis advisor: Prof. James Larus\nCo-examiner: Prof. Ed
 ouard Bugnion\n\nAbstract\nImproving the cost\, energy\, and performance o
 f our computing infrastructure has become increasingly challenging since t
 he demise of Moore's law and Dennard scaling. The industry is in need of i
 nnovation as general-purpose processors now experience an annual performan
 ce increase of only 2-10\\%\, far less than the growth rate of data we ask
  them to process. In response to these challenges\, many startups and even
  industry giants have started to develop hardware accelerators to bridge t
 his performance gap and obtain multi-fold speedups on their specific workl
 oads. This report presents two datacenter-scale deployment studies of such
  devices as well as the design of a standalone accelerator for a bioinform
 atics application.\n\nBackground papers\nDarwin: A Genomics Co-processor P
 rovides up to 15\,000X Acceleration on Long Read Assembly\, by Turakhia Y.
  et al.\nIn-Datacenter Performance Analysis of a Tensor Processing Unit\, 
 by Jouppi N.\, et al.\nA cloud-scale acceleration architecture\, by Caulfi
 eld A. et al.\n\n \n\n 
LOCATION:BC 229 https://plan.epfl.ch/?room==BC%20229
STATUS:CONFIRMED
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