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BEGIN:VEVENT
SUMMARY:On Fixed FPGA Interconnect
DTSTART:20180705T143000
DTEND:20180705T163000
DTSTAMP:20260407T091619Z
UID:4a5c4f4d797ea5a7cfc069c865decbc60c9b8898f71a3a8a2ce2167d
CATEGORIES:Conferences - Seminars
DESCRIPTION:Stefan Nikolic\nEDIC candidacy exam\nExam president: Prof. Gio
 vanni De Micheli\nThesis advisor: Prof. Paolo Ienne\nCo-examiner: Prof. Mi
 chael Kapralov\n\nAbstract\nThis report presents three papers related to t
 he problem of reducing FPGA interconnect flexibility by introduction of fi
 xed connections. One of them provides motivation for such endeavor\, while
  the others address scalability issues in the context of CAD tools and des
 ign space exploration. Finally\, a brief discussion on future work in this
  area is included.\n\nBackground papers\nBalancing interconnect and comput
 ation in a reconfigurable computing array (or\, why you don't really want 
 100% LUT utilization)\, A. DeHon\, in Proceedings of the 1999 ACM/SIGDA se
 venth international symposium on Field programmable gate arrays (FPGA '99)
 \, ACM\, New York\, NY\, USA\, 69-78.\nGlobal network alignment using mult
 iscale spectral signatures\,  R. Patro and C. Kingsford\, in Bioinformati
 cs\, vol. 28\, no. 23 (December 2012)\, 3105-3114.\nPolynomial time analys
 is of toroidal periodic graphs\, F. Höfting and E. Wanke\, in Abiteboul 
 S.\, Shamir E. (eds) Automata\, Languages and Programming\, ICALP 1994\, L
 ecture Notes in Computer Science\, vol 820\, Springer\, Berlin\, Heidelber
 g
LOCATION:INF 117 https://plan.epfl.ch/?room=INF117
STATUS:CONFIRMED
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