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SUMMARY:EE-SRI: Nanolithography and CAD Challenges beyond-14nm
DTSTART:20120622T161500
DTEND:20120622T171500
DTSTAMP:20260511T050438Z
UID:3e564dcb19b3da2728bd0d47b884e50dd0fb82c3105db3f8c8a7dd51
CATEGORIES:Conferences - Seminars
DESCRIPTION:David Pan\, University of Texas at Austin\nAs technology scale
 s to 22nm\, 14nm\, 11nm and possibly beyond (e.g.\, EE Times article on 10
 /26/2011 TSMC's R&D chief sees 10 years of scaling)\, new nanolithography 
 process technologies (including double/multiple patterning\, EUV\, E-beam 
 lithography) have to be developed to keep pace of the scaling. These\, cou
 pled with process variations\, leakage\, and reliability issues will add m
 ore complexity and cost into the already-challenging design closure. In th
 is talk\, I will present some key challenges/issues and recent research re
 sults on design for manufacturing (DFM) with these nanolithography technol
 ogies\, including layout decomposition with multiple patterning\, E-beam l
 ithography throughput improvement\, litho-hotspot detection and litho-frie
 ndly physical designs.
LOCATION:Room MXF1
STATUS:CONFIRMED
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