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SUMMARY:EE Distinguished Speakers Seminar Series: Nanoscale III-V Electron
 ics: InGaAs FinFETs and Vertical Nanowire MOSFETs
DTSTART:20190222T131500
DTSTAMP:20260528T020244Z
UID:a9cd5a11ed1d97216e98accb1f8dee3afad1ff4ba634e8c09c515f46
CATEGORIES:Conferences - Seminars
DESCRIPTION:Jesús A. del Alamo\, Professor of Electrical Engineering and 
 Director of the Microsystems Technology Laboratories\, Massachusetts Inst
 itute of Technology. \nAbstract\nIn the last few years\, as Si electronic
 s faces mounting difficulties to maintain its historical scaling path\, II
 I-V compound semiconductors have received a great deal of attention as pos
 sible alternatives. Sub-10 nm CMOS require high-aspect ratio 3D transistor
 s with a fin or nanowire geometry. The enhanced degree of channel charge c
 ontrol of advanced 3D designs allows for transistor size scaling to extrem
 ely small dimensions. At MIT\, we are investigating the prospects of nanos
 cale InGaAs FinFETs and vertical nanowire (VNW) MOSFETs fabricated through
  a top-down approach. We have demonstrated devices with sub-10 nm critical
  dimensions and record electrical characteristics. More recently\, we have
  developed thermal atomic-layer etching (TALE) for InGaAs and InAlAs. We h
 ave shown that in-situ integration of TALE with atomic layer deposition of
  the gate dielectric allows the fabrication of the gate stack without expo
 sure to air. This has yielded the most scaled InGaAs FinFETs to date with 
 sub-3 nm fin widths and record ON-and OFF-state characteristics. Our studi
 es reveal OFF-state leakage current\, mobility degradation and gate oxide 
 trapping as major stumbling blocks for future use of InGaAs 3D transistors
  in logic applications. This talk will review these and other problematic
  issues with III-V CMOS and discuss possible solutions.
LOCATION:ELA 002 https://plan.epfl.ch/?room=ELA002
STATUS:CONFIRMED
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