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SUMMARY:Challenges in Nanoelectronic Devices and Integrations on Silicon P
 latform Today and Tomorrow
DTSTART:20111010T161500
DTSTAMP:20260609T230137Z
UID:e7f884bb48579ca359ffb6f47f8ee2e263f0807ffe3913e097aeab38
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Yoshio Nishi\, Stanford University\nThere is widely shar
 ed concern today that as we approach future technology nodes of CMOS beyon
 d sub-20nm\, diminishing return in device performance and density combined
  with serious increase in on-chip power consumption would force us to seek
  for possible alternatives beyond simple scaling of the minimum geometry. 
 Applications of mechanical strain to MOSFET channel for improved transport
  characteristics\, material alternatives for conductive channel of MOSFET 
 such as germanium and/or III-V semiconductor\, intensive study for partial
  replacement of on-chip interconnects with optical interconnect\, new nonv
 olatile memory phenomena thereby feasibility of new memory devices such as
  resistive switching are only a part of such efforts in addition to global
  trend of going 3D devices and integration. Also mentioned should include 
 a variety of “nano” materials such as carbon nanotube\, graphene etc\,
  which might capture unique positions in an integrated circuit technology 
 arsenal with further in-depth understanding and technological break-throug
 h for controlling their characteristics. This talk will discuss a perspect
 ive of a variety of nanoelectronic devices to be integrated on silicon pla
 tform\, and where they would likely be heading toward.
LOCATION:INM200
STATUS:CONFIRMED
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