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SUMMARY:Logic Synthesis for Tunable Polarity FETs
DTSTART:20120911T110000
DTSTAMP:20260510T053554Z
UID:7413f976736175850e11b637ee6843083bbe303e86bf2ec2ec917ae6
CATEGORIES:Conferences - Seminars
DESCRIPTION:Mr. Luca Gaetano Amarù\nEDIC Candidacy Exam:\nExam president:
  Prof. Yusuf Leblebici\nThesis director: Prof. Giovanni de Micheli\nThesis
  co-director: Prof. Andreas Burg\nCo-examiner: Prof. David Atienza\n\nRese
 arch Proposal\n\nAn Efficient Gate Library for Ambipolar CNTFET Logic by B
 en-Jamaa\, M.H.\, K. Mohanram and G. De Micheli.\nImproving XOR-Dominated 
 Circuits by Exploiting Dependencies between Operands by A.K. Verma and P. 
 Ienne.\nTechnology Mapping for High-Performance Static CMOS and Pass Trans
 istor Logic Designs by Y.Jiang\, S.S. Sapatnekar and C.Bamjii.
LOCATION:INF328 http://plan.epfl.ch/
STATUS:CONFIRMED
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