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SUMMARY:Methods for detection\, prevention\, and protection from physical 
 side-channel attacks in remote FPGAs
DTSTART:20190612T090000
DTEND:20190612T110000
DTSTAMP:20260407T100403Z
UID:8668c750c0b571795009bce25a27c0bcb4e9d4c0794144f2a7c9db0c
CATEGORIES:Conferences - Seminars
DESCRIPTION:Ognjen Glamocanin\nEDIC candidacy exam\nExam president: Prof. 
 James Larus\nThesis advisor: Prof. Babak Falsafi\nThesis co-advisor: Dr. M
 irjana Stojilovic\nCo-examiner: Prof. Mathias Payer\n\nAbstract\nRecently 
 developed mechanisms for remote measuring of voltage drops inside the clou
 d FPGAs have made it possible to conduct power side-channel attacks on sha
 red FPGAs. In other words\, while one user of the FPGA is encrypting data 
 using a cryptographic IP core\, another (malicious) user is able to record
  the power consumption of the FPGA. Using this side-channel information\, 
 a set of standard power analysis attacks can be executed to try to recover
  the secret key. During my first project at PARSA\, I have demonstrated a 
 successful remote power-analysis attack. Besides side-channel attacks\, it
  was recently shown that a remote denial-of-service attack (using fault-in
 jection) or even a more subtle timing attack (by disturbing FPGA voltage) 
 may be successfully executed. These findings opened up fresh research oppo
 rtunities\, as many questions are still left unanswered: can we protect FP
 GA users from these attacks and can we do it without paying too high a pri
 ce in area\, performance\, or power consumption? Can we improve the FPGA c
 ompilation flow to detect malicious code? Can we detect a malicious activi
 ty on the fly? What other security risks may be out there\, waiting to be 
 discovered?\n\nBackground papers\nDifferential Power Analysis\, by Paul Ko
 cher\, Joshua Jaffe\, and Benjamin Jun CRYPTO 1999.\nAn Inside Job: Remot
 e Power Analysis Attacks on FPGAs\, by Falk Schellenberg\, Dennis R.E. Gna
 d\, Amir Moradi\, and Mehdi B. Tahoori\, DATE 2018.\nA Logic Level Design 
 Methodology for a Secure DPA Resistant ASIC or FPGA Implementation\, by Kr
 is Tiri and Ingrid Verbauwhede\, DATE 2004.\n\n 
LOCATION:BC 229 https://plan.epfl.ch/?room==BC%20229
STATUS:CONFIRMED
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