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SUMMARY:Security-centric processor design
DTSTART:20190621T090000
DTEND:20190621T110000
DTSTAMP:20260406T153022Z
UID:97ecca6e854984e0ce7646b4ff4c0ab38f1f6ec57810946ad62e7124
CATEGORIES:Conferences - Seminars
DESCRIPTION:Atri Bhattacharyya \nEDIC candidacy exam\nExam president: Pro
 f. Paolo Ienne\nThesis advisor: Prof. Babak Falsafi\nThesis co-advisor: Pr
 of. Mathias Payer\nCo-examiner: Prof. James Larus\n\nAbstract\nComputer ar
 chitectures are generally described by a set of architecturally defined re
 gisters and instructions which operate on and modify the state defined by 
 these registers. This abstraction\, called the Instruction Set Architectur
 e (ISA) abstracts away the microarchitectural details of processors implem
 enting it. Details that visibly affect the timing of the defined operation
 s are often abstracted away as well. Side-channel attacks leverage such ar
 chitecturally undefined "€œside-effects" to leak information.\nThis pape
 r describes two such attacks\, targeting the caching layer and speculative
  execution followed by a SOTA cache implementation that better matches the
  ISA abstraction\, preventing speculative loads from having any cache-effe
 cts. Finally\, it describes a proposal for further research towards bridgi
 ng the gap between microarchitecture and its abstraction\, with the aim of
  plugging this "leaky" abstraction.\n\nBackground papers\nCache attacks an
 d countermeasures: the case of AES\, by Osvik\, Dag Arne\, Adi Shamir\, an
 d Eran Tromer.\nSpectre attacks: Exploiting speculative execution\, by Koc
 her\, Paul\, et al.\nInvisispec: Making speculative execution invisible in
  the cache hierarchy\, by Yan\, Mengjia\, et al.\n 
LOCATION:BC 229 https://plan.epfl.ch/?room==BC%20229
STATUS:CONFIRMED
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