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SUMMARY:System Seminar : Scaling the Memory Wall with Phase Change Memorie
 s
DTSTART:20120627T133000
DTEND:20120627T143000
DTSTAMP:20260407T230422Z
UID:ef099d5017b3c2cf2568a3be642f99fffdf7494470608f7e314c6420
CATEGORIES:Conferences - Seminars
DESCRIPTION:Dr. Moinuddin Qureshi\nAs conventional memory technologies suc
 h as DRAM run into the scaling wall\, architects and system designers are 
 forced to look at alternative technologies for building\nfuture computer s
 ystems. Several emerging Non-Volatile Memory (NVM) technologies such as PC
 M\, STT-RAM\, and Memristors have the potential to boost memory capacity i
 n a scalable and power-efficient manner. However\, these technologies are 
 not drop-in replacements and will require novel solutions to enable their 
 deployment. Even the prime candidates among these technologies have their 
 own set of challenges such as higher read latency (than DRAM)\, much highe
 r write latency\, and limited write endurance. In this talk\, I will discu
 ss some of our recent work that addresses these challenges. Our solutions 
 include: hybrid memory systems\, start-gap wear leveling\, online attack d
 etection\, and efficient error correction. These solutions are applicable 
 to a wide variety of emerging NVM technologies\, and lay the groundwork fo
 r enabling their adoption in a broad spectrum of computer systems.\n\nBio:
 \nDr. Moinuddin Qureshi joined the faculty of the Georgia Institute of Tec
 hnology as an Associate Professor in August 2011. His research interests i
 nclude computer architecture\, scalable memory systems\, fault tolerant co
 mputing\, and analytical modeling of computer systems. He worked as a rese
 arch staff member at IBM T.J. Watson Research Center from 2007 to 2011. Wh
 ile at IBM\, he contributed to the design of efficient caching algorithms 
 for Power 7 processors. He was awarded the IBM outstanding technical achie
 vement award for his studies on emerging memory technologies for server pr
 ocessors. He received his Ph.D. (2007) and M.S. (2003)\, both in Electrica
 l Engineering from the University of Texas at Austin\, and his Bachelor of
  Electronics Engineering (2000) degree from University of Mumbai.
LOCATION:BC 410 https://plan.epfl.ch/?room==BC%20410
STATUS:CONFIRMED
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