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SUMMARY:EE Seminar: From Deep Scaling to Deep Intelligence
DTSTART:20190726T140000
DTEND:20190726T150000
DTSTAMP:20260511T113855Z
UID:4e8e85ab728ba66e846c1657493210bdcd5f81ed02ab0321a4c34bee
CATEGORIES:Conferences - Seminars
DESCRIPTION:Dr. Rajiv V. Joshi is a research staff member and key technica
 l lead at T. J.Watson research center\, IBM. He received his B.Tech I.I.T 
 (Bombay\, India)\, M.S (M.I.T) and Dr. Eng. Sc. (Columbia University). His
  novel interconnects processes and structures for aluminum\, tungsten and 
 copper technologies which are widely used in IBM for various technologies 
 from sub-0.5μm to 14nm. He has led successfully predictive failure analyt
 ic techniques for yield prediction and also the technology-driven SRAM at 
 IBM Server Group. He has extensively worked on novel memory designs. He co
 mmercialized these techniques. He received 3 Outstanding Technical Achieve
 ment (OTAs)\, 3 highest Corporate Patent Portfolio awards for licensing co
 ntributions\, holds 58 invention plateaus and has over 225 US patents and 
 over 350 including international patents. He has authored and co-authored 
 over 190 papers. He has given over 45 invited/keynote talks and given seve
 ral Seminars. He is awarded prestigious IEEE Daniel Noble award for 2018. 
 He received the Best Editor Award from IEEE TVLSI journal. He is recipient
  of 2015 BMM award. He is inducted into New Jersey Inventor Hall of Fame i
 n Aug 2014 along with pioneer Nicola Tesla. He is a recipient of 2013 IEEE
  CAS Industrial Pioneer award and 2013 Mehboob Khan Award from Semiconduct
 or Research Corporation. He is a member of IBM Academy of technology. He s
 erved as a Distinguished Lecturer for IEEE CAS and EDS society. He is Dist
 inguished visiting professor at IIT\, Roorkie. He is IEEE\, ISQED andWorld
  Technology Network fellow and distinguished alumnus of IIT Bombay. He is 
 in the Board of Governors for IEEE CAS. He serves as an Associate Editor o
 f TVLSI. He served on committees of ISCAS 2017\, ISLPED (Int. Symposium Lo
 w Power Electronic Design)\, IEEE VLSI design\, IEEE CICC\, IEEE Int. SOI 
 conference\, ISQED and Advanced Metallization Program committees. He serve
 d as a general chair for IEEE ISLPED. He is an industry liaison for univer
 sities as a part of the Semiconductor Research Corporation. Also\, he is i
 n the industry liaison committee for IEEE CAS society. \nAbstract : Moor
 e’s law driving the advancement in semiconductor industry over decades h
 as been coming to a screeching halt and many researchers are convinced tha
 t it is almost dead. After revival and promise of artificial intelligence 
 (AI) due to increased computational performance and memory bandwidth aided
  by Moore’s law there is overwhelming enthusiasm in researchers for incr
 easing the pace of VLSI industry. AI uses many neural network techniques f
 or computation which involves training and inference.\nThe advancement in 
 AI requires energy efficient\, low power hardware systems. This is more so
  for servers\, main processors\, Internet of Things (IoT) and System on ch
 ip (SOC) applications and newer applications in cognitive computing. In th
 e light of AI this talk focuses on advanced technology issues\, important 
 circuit techniques for lowering power\, improving performance and function
 ality in nanoscale VLSI design in the midst of variability. The same techn
 iques can be used for AI specific accelerators.\nAccelerator development f
 or reduction in power and throughput improvement for both edge and data ce
 ntric accelerators compared to GPUs used for Convolutional Neural (CNN) an
 d Deep Neural (DNN) Networks are described. The talk covers memory (volati
 le and nonvolatile) solutions for CNN/DNN applications at extremely low Vm
 in. Finally\, the talk summarizes challenges and future directions for cir
 cuit applications for edge and data-centric accelerators.\n 
LOCATION:INF 328 https://plan.epfl.ch/?room=INF328
STATUS:CONFIRMED
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