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SUMMARY:EE Distinguished Speakers Seminar: VLSI Sensors and Security
DTSTART:20191018T131500
DTEND:20191018T141500
DTSTAMP:20260930T201205Z
UID:a421193bb1cfee4cfc58c194071ce8803f29c793a8e0d4f4fedcd6ec
CATEGORIES:Conferences - Seminars
DESCRIPTION:Wayne Burleson has been a Professor of Electrical and Computer
  Engineering at the University of Massachusetts Amherst since 1990. From 2
 012-2017 he was also Senior Fellow at AMD Research in Boston working on po
 wer optimization\, especially for supercomputing under the DOE FastForward
  and DesignForward programs.  He has degrees from MIT and the University
  of Colorado.  He has worked as a custom chip designer and consultant in
  the semiconductor industry with VLSI Technology\, DEC\, Compaq/HP\, Intel
 \, Rambus and AMD.  Wayne was a visiting professor at ENST Paris in 1996
 /97\, at LIRM Montpellier in 2003 and at EPFL Switzerland in 2010/11. His 
 research is in the general area of VLSI\, including circuits and CAD for l
 ow-power\, long interconnects\, clocking\, reliability\, thermal effects\,
  process variation and noise mitigation. He also conducts research in hard
 ware security\, reconfigurable computing\, content-adaptive signal process
 ing\, RFID and multimedia instructional technologies.   He teaches cour
 ses in VLSI Design\, Embedded Systems and Security Engineering.  Wayne h
 as published over 200 refereed publications in these areas and is a Fello
 w of the IEEE for contributions in integrated circuit design and signal pr
 ocessing.\nAbstract: Very Large Scale integrated circuits use multiple lev
 els of abstraction to hide physical behavior beneath a digital façade. 
  In particular\, manufacturing process variations\, aging effects\, volta
 ge noise and thermal variations\, must be modeled at design time and manag
 ed at run-time in order to provide efficient and reliable computation.  
 These effects are all increasing as CMOS technology advances\, and are pre
 sent in most post-CMOS technologies as well.  These same physical variat
 ions can be used as sources of entropy and unique identifiers to provide a
  foundation of trust to support higher level security protocols.  This t
 alk will introduce a variety of on-chip sensors in both custom CMOS and FP
 GA technologies that use statistical techniques to measure various physica
 l quantities at very fine-grain spatial and temporal granularity.  New c
 ircuits will be shown to securely deliver random numbers and chip identifi
 ers even in the presence of powerful adversaries.  A proposal for “sec
 ret-free” cryptography based on hardware will also be explored which pro
 tects against an even stronger threat model.  Finally\, a new undergradu
 ate lab course in Security Engineering will be presented\, showing how VLS
 I and embedded system design can be taught in the context of an intelligen
 t adversary.\n 
LOCATION:MXF 1 https://plan.epfl.ch/?room==MXF%201
STATUS:CONFIRMED
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