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SUMMARY:Power is Money: Spend it wisely - (Or\, Scalable Cores and Caches 
 for Power-Constrained CMPs)
DTSTART:20120918T161500
DTEND:20120918T171500
DTSTAMP:20260504T041736Z
UID:39cf6f80c4cab9f4741e6371fbe81fc09de5d42bd48d89d8dbd36f82
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. David A. Wood\nAbstract : Moore's Law continues to pro
 vide exponential growth in transistor density\, but the end of Denard Scal
 ing means that a decreasing fraction of transistors can be simultaneously 
 active. As a result\, power has become arguably the most critical resource
  in computer systems design. Moreover\, future chip multiprocessor (CMP) s
 ystems must support dynamic power budgeting\, so that power can be "spent"
  where it will provide the most (performance) benefit. Future CMPs must pr
 ovide scalable cores\, which scale down to exploit thread-level parallelis
 m when software provides enough threads to run\, and scale up to deliver h
 igh single-thread performance--via instruction-level and memory-level para
 llelism--to mitigate sequential bottlenecks and/or to guarantee service-le
 vel agreements.  Similarly\, future CMPs must use scalable caches\, which
  scale up to reduce misses and memory power\, or scale down---by reducing 
 capacity and associativity---when power is better spent by the cores.\nThi
 s talk will discuss the Wisconsin Multifacet project's work on scalable co
 res and caches to enable power budgeting. WiDGET (Wisconsin Decoupled Grid
  Execution Tiles) is a scalable core that decouples thread context managem
 ent from a sea of simple execution units. Forwardflow is an alternative co
 re architecture that dynamically builds an explicit internal dataflow repr
 esentation from a conventional instruction set architecture\, using forwar
 d dependence pointers to guide instruction wakeup\, selection\, and issue.
  Both WiDGET and Forwardflow provide the flexibility to achieve a particul
 ar power-performance target by power-gating unallocated computation resour
 ces. Finally\, this talk will touch on recent work on dynamically determin
 ing the optimal cache configuration for a given workload.\n\nBio : Prof. D
 avid A. Wood is a Professor in the Computer Sciences Department at the Uni
 versity of Wisconsin\, Madison and has a joint appointment in Electrical a
 nd computer Engineering. Dr. Wood was named an ACM Fellow (2005) and IEEE 
 Fellow (2004)\, received the University of Wisconsin's H.I. Romnes Faculty
  Fellowship (1999)\, received the National Science Foundation's Presidenti
 al Young Investigator award (1991)\, and earned his Ph.D. in Computer Scie
 nces from the University of California\, Berkeley (1990). Dr. Wood is Chai
 r of ACM Special Interest Group on Computer Architecture (SIGARCH)\, Area 
 Editor (Computer Systems) of ACM Transactions on Modeling and Computer Sim
 ulation\, is Associate Editor of ACM Transactions on Architecture and Comp
 iler Optimization\, served as Program Committee Chairman of ASPLOS-X (2002
 )\, and has served on numerous program committees. Dr. Wood is an ACM Fell
 ow\, an IEEE Fellow\, and a member of the IEEE Computer society. Dr. Wood 
 has published over 70 technical papers and is an inventor on over a dozen 
 U.S. and International patents.\nDr. Wood co-leads the Wisconsin Multiface
 t project with Prof. Mark Hill (URL http://www.cs.wisc.edu/multifacet) whi
 ch is exploring techniques for improving the availability\, designability\
 , programmability\, and performance of commercial multiprocessor and chip 
 multiprocessor servers. 
LOCATION:BC 410 https://plan.epfl.ch/?room==BC%20410
STATUS:CONFIRMED
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