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VERSION:2.0
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SUMMARY:Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP) w
 ith AI engines
DTSTART:20200123T111500
DTEND:20200123T121500
DTSTAMP:20260407T083353Z
UID:8b2181cabbd97b8d5ea589411dfbe8921c1ce1a3aa6f7f649d3ca435
CATEGORIES:Conferences - Seminars
DESCRIPTION:Kees Vissers and Stephen Neuendorffer (Xilinx Research\, San J
 ose\, CA\, USA)\n \nIn this presentation we will present the new Adaptive
  Compute Acceleration Platform. We will show the overall system architectu
 re of the family of devices including the Arm cores (scalar engines)\, the
  programmable logic (Adaptable Engines) and the new vector processor cores
  (AI engines). We will focus on the new AI engines in more detail and show
  the architecture\, the integration in the total device\, the programming 
 environment and some applications\, including Machine Learning and 5G wire
 less applications. The latest Silicon device contains 400 of these novel v
 ector processor cores. We will present the direction of new research inclu
 ding the mapping of algorithms and machine learning applications to these 
 multi-core systems.\n\nKees Vissers graduated from Delft University in the
  Netherlands. He worked at Philips Research in Eindhoven\, the Netherlands
 \, for many years. The work included Digital Video system design\, HW –S
 W co-design\, VLIW processor design and dedicated video processors. He was
  a visiting industrial fellow at Carnegie Mellon University and at UC Berk
 eley. He is heading a team of researchers at Xilinx. The research topics i
 nclude next generation programming environments for processors and FPGA fa
 bric\, high-performance video systems\, machine learning applications and 
 architectures\, wireless applications and datacenter applications. He has 
 been instrumental in the High-Level Synthesis technology and one of the te
 chnical leads in the novel array of AI engines.\n\nStephen Neuendorffer gr
 aduated from UC Berkeley. He has worked at Xilinx for 14 years on various 
 aspects of system design for FPGAs\, including 5 years as product architec
 t of Vivado HLS.  He is currently working in the Xilinx Research Labs wit
 h a focus on machine learning and next-generation devices.  
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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