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SUMMARY:Logic Synthesis and Optimization for Emerging Technologies
DTSTART:20210628T140000
DTEND:20210628T160000
DTSTAMP:20260501T205815Z
UID:f1cb9a98054cf55130b9d1162998201215ab54f2cc66785cf6d1f7eb
CATEGORIES:Conferences - Seminars
DESCRIPTION:Dewmini  Marakkalage \nEDIC candidacy exam\nexam president: 
 Prof. Paolo Ienne\nthesis advisor: Prof. Giovanni De Micheli\nco-examiner:
  Prof. Andreas Burg\nexpert: Dr. Heinz Riener\n\nAbstract\nThe existing di
 gital logic synthesis tools are tailored to the needs of complementary met
 al-oxide-semiconductor (CMOS) technology which has been the dominant elect
 ronics technology for decades.\nHowever\, enabled by recent technological 
 advancements and fueled by the drive for high-speed energy-efficient compu
 tation\, alternate forms of electronic technologies such as superconductin
 g electronics (SCE) are gaining pace.\nThe existing CMOS-specific synthesi
 s tools\, however\, are unable to fully exploit the benefits of such techn
 ologies as such tools are not optimized for these technologies and are not
  equipped to deal with the additional constraints such as clocked logic ga
 tes they impose.\nIn this research proposal\, we first look at one recentl
 y proposed synthesis flow for a particular superconducting technology call
 ed adiabatic quantum-flux-parametron (AQFP).\nWe then look at a versatile 
 synthesis approach called SAT-based exact synthesis which seems promising 
 as a tool for synthesizing optimal circuit structures under various constr
 aints for functions of a few variables and study how that approach could h
 elp the synthesis algorithms for larger logic networks in emerging technol
 ogies.\nIn this regard\, we also study a depth-optimal polynomial-time rew
 riting algorithm for FPGA technology mapping that has wider implications a
 nd discuss its benefits and drawbacks.\nWe finally propose a high-level ov
 erview of our research plan which broadly aims at developing new logic syn
 thesis algorithms targeting post-CMOS technologies.\n\nBackground papers\n
 1. "A semi-custom design methodology and environment for implementing supe
 rconductor adiabatic quantum-flux-parametron microprocessors"\,\n https:/
 /iopscience.iop.org/article/10.1088/1361-6668/ab7ec3/meta\n2. "SAT-Based E
 xact Synthesis: Encodings\, Topology Families\, and Parallelism" https://i
 eeexplore.ieee.org/abstract/document/8634910?casa_token=J7M9Rn-prBYAAAAA:w
 D0RbwerD2BzV9T8cYW4-o3zguu8FvC4Lv1r8u_qXT2Mys05_jmu87TF4Trj9zAOkeLQkbnSFw\
 n3. "FlowMap: an optimal technology mapping algorithm for delay optimizati
 on in lookup-table based FPGA designs"\nhttps://ieeexplore.ieee.org/abstra
 ct/document/273754\n\n\n\n 
LOCATION:
STATUS:CONFIRMED
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