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SUMMARY:Logic design and technology mapping for superconducting circuits
DTSTART:20210628T153000
DTEND:20210628T173000
DTSTAMP:20260406T185314Z
UID:dc0d056f405e8958f03ae84151d583adddcae1c411f9436e12f5d7bc
CATEGORIES:Conferences - Seminars
DESCRIPTION:Alessandro Tempia Calvino\nEDIC candidacy exam\nexam president
 : Prof. Viktor Kuncak\nthesis advisor: Prof. Giovanni De Micheli\nco-exami
 ner: Prof. Catherine Dehollain\nexpert: Dr. Heinz Riener\n\nAbstract\nSupe
 rconducting electronics (SCE) gained recent interest by proposing scalable
  and power-efficient solutions to overcome the limitations and challenges 
 of CMOS technology in reducing energy consumption. SCE logic such as rapid
  single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) d
 iffers from standard CMOS electronics in several aspects introducing new c
 onstraints that electronic design automation (EDA) tools have to support. 
 In particular\, logic gates are clocked elements\, data is required to be 
 available in specific time-frames\, and branching elements are necessary t
 o drive multiple cells. State-of-the-art logic synthesis tools describe a 
 circuit using technology-independent representations\, apply logic optimiz
 ations\, and map into a technology-dependent representation. In this propo
 sal\, the transformation of a technology-independent logic circuit to an o
 ptimized technology-dependent one is reviewed. First\, the fundamentals of
  technology mapping and how to obtain a good technology-independent graph 
 structure suitable for mapping are introduced. Then\, a remapping techniqu
 e to further improve a circuit accounting for technology constraints is pr
 esented. Next\, an architecture for single-flux-quantum (SFQ) circuits is 
 analyzed. Finally\, possible research directions focusing on logic synthes
 is techniques for SCE are proposed.\n\nBackground papers\n\n1)    "Redu
 cing structural bias in technology mapping”\, by  S. Chatterjee\, A. Mi
 shchenko\, R. Brayton\, X. Wang and T. Kam\n         https://ieeex
 plore.ieee.org/document/1560122\n2)      “Iterative remapping for l
 ogic circuits"\, by L. Benini\, P. Vuillod and G. De Micheli\n      
    https://ieeexplore.ieee.org/document/728916\n3)       “An Eff
 icient Pipelined Architecture for Superconducting Single Flux Quantum Logi
 c Circuits Utilizing Dual Clocks"\, by G. Pasandi and M. Pedram\n    
      https://ieeexplore.ieee.org/document/8910442
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STATUS:CONFIRMED
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