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SUMMARY:A Unified Frontend Processor Architecture
DTSTART:20210624T110000
DTEND:20210624T130000
DTSTAMP:20260407T002702Z
UID:cc52ddcecec622da74088da28415d067ac1b49272d05aee065f5fd3e
CATEGORIES:Conferences - Seminars
DESCRIPTION:Ali Ansari\nEDIC candidacy exam\nexam president: Prof. James L
 arus\nthesis advisor: Prof. Babak Falsafi\nco-examiner: Prof. Paolo Ienne\
 n\nAbstract\nThe frontend bottleneck is a well-known source of\nperformanc
 e degradation in modern processors. Server workloads’\nworking sets reac
 h multi-megabytes that defy limited\ncapacity L1 instruction cache (L1-I) 
 and branch target buffer\n(BTB). Frequent misses in these components cause
  poor instruction\nsupply for the core backend and performance loss. To\na
 ddress this problem\, researchers have proposed a myriad of\nprefetching t
 echniques. Predicting the control flow ahead of the\nfetch stream has been
  the main insight in these solutions. Earlier\nwork tackled L1-I and BTB m
 isses separately. But recent work\nhas shown that both problems can be sol
 ved at the same time\nusing a unified prefetching scheme.\nIn this write-u
 p\, we study three papers\, Confluence (MICRO-\n2015)\, Boomerang (HPCA-20
 17)\, and Shotgun (ASPLOS-2018)\,\nthat investigate control flow predictio
 n to offer unified solutions\nfor the frontend bottleneck. This study will
  help us to become\nfamiliar with the main challenges in this domain and p
 ossible\nopportunities for follow-up work. According to these papers\,\nwe
  conclude that an effective BTB design is the key to have\na powerful fron
 tend.\n\nBackground papers\nConfluence: unified instruction supply for sca
 le-out servers\nBoomerang: A metadata-free architecture for control flow
  delivery\nBlasting through the front-end bottleneck with shotgun
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STATUS:CONFIRMED
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