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SUMMARY:FPGA-Accelerated Performance Model for Architecture Research
DTSTART:20210701T150000
DTEND:20210701T170000
DTSTAMP:20260407T064350Z
UID:7d96f2806c71ecc7692a5b3594b2054f43a1fa7d75f8bad3b6029a04
CATEGORIES:Conferences - Seminars
DESCRIPTION:Shanqing Lin\nEDIC candidacy exam\nexam president: Prof. James
  Larus\nthesis advisor: Prof. Babak Falsafi\nco-examiner: Prof. Paolo Ienn
 e\n\nAbstract\nMicroarchitecture simulators are essential tools for system
  research\, and software simulators suffer from their limited performance 
 due to the finer parallelism in the model's implementation. FPGAs are natu
 rally applied to accelerate simulation to gain more throughput due to thei
 r capacity to exploit fine-grained parallelism. This report will examine t
 hree paradigms of FPGA-accelerated simulators and their evolution on perfo
 rmance and accuracy. Two directions\, including scale-out simulation and d
 omain-specific representations\, are also proposed to improve performance\
 , accuracy\, and usability.\n\nBackground papers\nUT-FAST: https://ieeexpl
 ore.ieee.org/abstract/document/4408260\nRamp Gold: https://dl.acm.org/doi/
 abs/10.1145/1815961.1815999\nHASim: https://ieeexplore.ieee.org/abstract/d
 ocument/5749747\n 
LOCATION:
STATUS:CONFIRMED
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