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SUMMARY:Beyond ILP for FPGA-based HLS Tools
DTSTART:20210722T120000
DTEND:20210722T140000
DTSTAMP:20260408T063611Z
UID:a8c860a80b181b41e23b994151e76deadf729be5006857c5d505ea05
CATEGORIES:Conferences - Seminars
DESCRIPTION:Ayatallah Elakhras\nEDIC candidacy exam\nexam president: Prof.
  Babak Falsafi\nthesis advisor: Prof. Paolo Ienne\nco-examiner: Prof. Davi
 d Atienza\n\nAbstract\nField Programmable Gate Arrays (FPGAs) are attracti
 ve\nplatforms for applications with high computational demands\nand low en
 ergy consumption requirements. However\, the\ndesign effort for FPGA devel
 opment remains high in comparison\nto that for software development. High-
 level synthesis (HLS)\ntools are meant to ease the process of FPGA develop
 ment by\ngenerating hardware designs from high level languages such\nas C/
 C++. However\, they do not always produce high quality\ndesigns\, especial
 ly for applications that can not be automatically\nparallelized easily. In
  this report we study existing research work\naimed at improving different
  steps in the HLS process towards\nbetter exploiting instruction-level par
 allelism (ILP) and easing\nthe design process. We conclude with a proposal
  for a research\ndirection we intend to take toward\n\nBackground papers\n
 1)  Title: Architecture and Synthesis for Area-Efficient Pipelining of Ir
 regular Loop Nests\n     Authors: Gai Liu\, Mingxing Tan\, Steve Dai\,
  Ritchie Zhao\, Zhiru Zhang\n     Link: https://ieeexplore.ieee.org/doc
 ument/7842548\n\n2)  Title: A compiler Infrastructure for Accelerator Gen
 erators\n     Authors: Rachit Nigam\, Samuel Thomas\, Zhijing Li\, Adr
 ian Sampson\n     Link: https://dl.acm.org/doi/abs/10.1145/3445814.3446
 712\n\n3)  Title: Chronos: Efficient Speculative Parallelism for Accelera
 tor\n     Authors: Maleen Abeydeera\, Daniel Sanchez\n     Link: ht
 tps://dl.acm.org/doi/abs/10.1145/3373376.3378454\n 
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STATUS:CONFIRMED
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