Specialized Processor Architecture for Datacentres

EDIC candidacy exam
Exam president: Prof. Paolo Ienne
Thesis advisor: Prof. Babak Falsafi
Co-examiner: Prof. Giovanni de Micheli

Abstract
In today's scale-out datacentres, understanding the interactions of the high level system with the underlying microarchitecture enables designers to extract more performance out of the hardware. This candidacy proposal focuses on one of the outstanding issues in processor design: the instruction supply mechanism. We survey real profiling data from a production Google datacentre to motivate the study, and show that today's processors take a suboptimal approach to both storing and prefetching instructions. Then, we cover two state-of the art instruction supply mechanisms presented in computer architecture literature, both of which target this problem. Although both mechanisms present valuable insights, we propose a new contribution, to design a specialized processor that better matches the constraints of scale-out computing. Finally, we present a blueprint for a next-generation datacentre processor, which shares its instruction state between all of the component cores, freeing up valuable die area and increasing overall performance density.

Background papers
Profiling a Warehouse Scale Computer, S. Kanev, J. P. Darago, K. Hazelwood, P. Ranganathan, T. Moseley, G.-Y. Wei, and D. Brooks.
Boomerang: a Metadata Free Architecture for Control Flow Delivery, R. Kumar, C.-C. Huang, B. Grot, and V. Nagarajan.
SHIFT: Shared History Instruction Fetch for Lean-core Server Processors, C. Kaynak, B. Grot, and B. Falsafi.