3D monolithic integration
Event details
| Date | 24.06.2010 |
| Hour | 16:00 |
| Speaker | Perrine Batude, CEA-LETI, Grenoble, France |
| Location |
INM 202
|
| Category | Conferences - Seminars |
Description 3D integration generates great interest to solve the fundamental limits of scaling e.g. increasing delay in interconnections, development costs and variability. 3D monolithic integration, by opposition to parallel (or back-end or TSV 3D integration) is the only technological option enabling to fully benefit from the third dimension potential at the transistor scale thanks to its high alignment precision (σMONO ~10nm compared to σTSV ~0.5µm ). The sequential processing of bottom and top FET is however challenging because of the potential detrimental impact on bottom FET of the top FET processing. During this presentation, an overview of Leti’s results in that field will be given.
Practical information
- General public
- Free
Contact
- Anil Leblebici