Memory Processing Units

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Event details

Date and time 19.09.2014 14:0015:15  
Place and room
Speaker Karu Sankaralingam, University of Wisconsin-Madison
Category Conferences - Seminars
3D die-stacking of logic and DRAM warrants revisiting the ideas of near-memory processing. We make the case for extending the current architectures with Memory Processing Units based on the commercially available HMC. On the programming model and execution side we propose memory remote-procedure calls to offload entire pieces of computation to MPU. On the hardware side we argue that non-speculating, low-frequency, ultra-short pipeline processing cores integrated closely with memory provide efficient processing. MPUs are applicable across a wide domain of workloads spanning data-intensive computing, networking, and SQL database processing. Compared to a conventional multicore, a system with MPUs using 128 ARM Cortex M3 micro-controllers per chip provides geometric mean 3.8X higher performance and 13X lower energy.

Practical information

  • Informed public
  • Free

Organizer

  • Babak Falsafi

Contact

  • Stéphanie Baillargues

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