Metrology for materials research and failure analysis in the semiconductor industry of the post-nanometer era

The naming conventions employed by leading semiconductor foundries to describe the next generation of nanoelectronics signal the dawn of the Angstrom era. The unit (Å) is used to measure atoms, and ionic radius with 1Å roughly equal to the diameter of one atom, or 0.1 nm. Although discrete manufacturing at this scale is still unattainable, the design of the upcoming logic and memory devices revolves around increasingly smaller architectures, incorporating three-dimensional structures and a wider range of materials.
Anticipated advancements in transistor design include the transition from FinFET to nanosheets at 2nm, followed by groundbreaking concepts like vertical, stackable, and chiplets architectures, and atomic channels at 1nm and beyond. Consequently, evaluating the properties of materials at the nanometer scale to establish correlations with device functionality, reliability, and failures presents a significant challenge for the scientific community. In this context, I will provide an overview of potential future scenarios for the roadmap, offering a comprehensive perspective on critical issues regarding materials integration and metrology. We will explore various areas of research in the semiconductor industry with emphasis on site-specific metrology.

Bio
Umberto Celano received the B.Eng. and M.Sc. degrees in Electrical Engineering from the Sapienza University of Rome, Italy, in 2009 and 2011, respectively, and the Ph.D. degree in Physics from the University of Leuven - KU Leuven in 2015. He is now Associate Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He is also metrology and characterization capability lead of the SWAP Hub for the Department of Defense Microelectronics Commons, and the materials characterization lead in the National Advanced Packaging Manufacturing Program SHIELD USA.
Before moving to ASU Umberto contributed in various roles to the process development and characterization of advanced CMOS materials (logic and memory), working as a principal member of technical staff at imec (Belgium), and part-time professor in the faculty of science and technology at the University of Twente (the Netherlands). In 2018, he was a visiting scientist with the Geballe Laboratory for Advanced Materials at Stanford University where he expanded his research interest to two-dimensional (2D) materials and nanophotonic. Previously, Umberto worked alongside Prof. Wilfried Vandervorst at the University of Leuven - KU Leuven and imec (Belgium). Here, he got interested in materials analysis and semiconductor metrology with emphasis on the correlation between device physics, materials properties, and failure analysis.