Fast Module-Based FPGA Compile Flow from High-Level Circuit Specifications

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Event details

Date 14.06.2017
Hour 16:3018:00
Speaker Mikhail Asiatici
Location
Category Conferences - Seminars

EDIC candidacy exam
Exam president: Prof. Giovanni De Micheli
Thesis advisor: Prof. Paolo Ienne
Co-examiner: Prof. David Atienza Alonso

Abstract
Two factors limit the mass adoption of Field Programmable Gate Arrays (FPGAs) beyond the hardware developers community: the non-traditional programming model, and the low design productivity due to compile times in the order of hours.
High-Level Synthesis (HLS) represents a promising solution to the first problem as it automatically generates hardware designs from high-level programming languages familiar to software developers.
To tackle the second problem, overlays and hard macros are two of the approaches that have been proposed.
Overlays are virtual programmable architectures implemented on the FPGA where applications can be mapped more easily than on the FPGA resources directly.
Hard macros are pre-processed modules that can be reused by the FPGA toolchain to quickly reimplement common functionalities.
Although both approaches can reduce FPGA compile times by up to 4 orders of magnitude, they impose important limitations on the structure of the designs they can handle and on the quality of the circuits they produce.
In this report, we build up on the results from the overlay and hard macro literature to propose new research directions to achieve fast FPGA compilation of arbitrary designs, specified in high-level languages, with minimal overheads.

Background papers
A high-performance overlay architecture for pipelined execution of data flow graphs. Field Programmable Logic and Applications (FPL),2013 23rd International Conference on. IEEE, 201,  by Capalija, Davor, and Tarek S. Abdelrahman.
Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts, IEEE Micro 34.1 (2014): 42-53, Coole J. and Grefg Stitt.
Design re-use for compile time reduction in FPGA high-level synthesis flows, Field-Programmable Technology (FPT), 2014 International Conference on. IEEE, 2014 by Gort, Marcel, and Jason Anderson.

 

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