A Unified Frontend Processor Architecture
Event details
| Date | 24.06.2021 |
| Hour | 11:00 › 13:00 |
| Speaker | Ali Ansari |
| Category | Conferences - Seminars |
EDIC candidacy exam
exam president: Prof. James Larus
thesis advisor: Prof. Babak Falsafi
co-examiner: Prof. Paolo Ienne
Abstract
The frontend bottleneck is a well-known source of
performance degradation in modern processors. Server workloads’
working sets reach multi-megabytes that defy limited
capacity L1 instruction cache (L1-I) and branch target buffer
(BTB). Frequent misses in these components cause poor instruction
supply for the core backend and performance loss. To
address this problem, researchers have proposed a myriad of
prefetching techniques. Predicting the control flow ahead of the
fetch stream has been the main insight in these solutions. Earlier
work tackled L1-I and BTB misses separately. But recent work
has shown that both problems can be solved at the same time
using a unified prefetching scheme.
In this write-up, we study three papers, Confluence (MICRO-
2015), Boomerang (HPCA-2017), and Shotgun (ASPLOS-2018),
that investigate control flow prediction to offer unified solutions
for the frontend bottleneck. This study will help us to become
familiar with the main challenges in this domain and possible
opportunities for follow-up work. According to these papers,
we conclude that an effective BTB design is the key to have
a powerful frontend.
Background papers
Confluence: unified instruction supply for scale-out servers
Boomerang: A metadata-free architecture for control flow delivery
Blasting through the front-end bottleneck with shotgun
exam president: Prof. James Larus
thesis advisor: Prof. Babak Falsafi
co-examiner: Prof. Paolo Ienne
Abstract
The frontend bottleneck is a well-known source of
performance degradation in modern processors. Server workloads’
working sets reach multi-megabytes that defy limited
capacity L1 instruction cache (L1-I) and branch target buffer
(BTB). Frequent misses in these components cause poor instruction
supply for the core backend and performance loss. To
address this problem, researchers have proposed a myriad of
prefetching techniques. Predicting the control flow ahead of the
fetch stream has been the main insight in these solutions. Earlier
work tackled L1-I and BTB misses separately. But recent work
has shown that both problems can be solved at the same time
using a unified prefetching scheme.
In this write-up, we study three papers, Confluence (MICRO-
2015), Boomerang (HPCA-2017), and Shotgun (ASPLOS-2018),
that investigate control flow prediction to offer unified solutions
for the frontend bottleneck. This study will help us to become
familiar with the main challenges in this domain and possible
opportunities for follow-up work. According to these papers,
we conclude that an effective BTB design is the key to have
a powerful frontend.
Background papers
Confluence: unified instruction supply for scale-out servers
Boomerang: A metadata-free architecture for control flow delivery
Blasting through the front-end bottleneck with shotgun
Practical information
- General public
- Free
Organizer
- EDIC