Address Translation without TLBs
Event details
| Date | 22.06.2021 |
| Hour | 09:00 › 11:00 |
| Speaker | Yuanlong Li |
| Category | Conferences - Seminars |
EDIC candidacy exam
exam president: Prof. James Larus
thesis advisor: Prof. Babak Falsafi
co-examiner: Prof. Sanidhya Kashyap
Abstract
Page-based virtual memory is widely used in modern computer systems. The hardware implements the virtual memory functionality by performing the virtual-to-physical address translations, which are accelerated by the Translation Lookaside Buffers (TLBs). Nevertheless, with the unprecedented capacity of the cache hierarchies of emerging big-memory systems, the TLBs cease to provide the required performance benefits because they fail to cover the application's working set. The TLBs cannot scale with the cache hierarchies due to the hardware constraints and latency requirements, leading to the TLB scalability issue. Our goal is to solve the TLB scalability issue by designing a scalable address translation scheme without TLBs.
In this proposal, we discuss three existing works that try to address the TLB scalability issue. First, we show that the address translation can be deferred until accessing the memory by adopting virtual cache and intermediate address space. Performing the address translation within the cache hierarchies helps in removing TLBs from the system. Then we illustrate the benefit of transparent large pages in improving the TLB coverage. Finally, we discuss how exploiting application-level semantics can result in a scalable TLB-free address translation scheme and our follow-up works to enhance the scheme.
Background papers
1. DA Wood et al: An in-cache address translation mechanism
https://dl.acm.org/doi/abs/10.1145/17356.17398
2. L Zhang et al: Enigma: architectural and operating system support for reducing the impact of address translation
https://dl.acm.org/doi/abs/10.1145/1810085.1810109
3. S Gupta et al: Rebooting Virtual Memory with Midgard (accepted to appear at ISCA '21)
https://infoscience.epfl.ch/record/285466/files/midgard.pdf
exam president: Prof. James Larus
thesis advisor: Prof. Babak Falsafi
co-examiner: Prof. Sanidhya Kashyap
Abstract
Page-based virtual memory is widely used in modern computer systems. The hardware implements the virtual memory functionality by performing the virtual-to-physical address translations, which are accelerated by the Translation Lookaside Buffers (TLBs). Nevertheless, with the unprecedented capacity of the cache hierarchies of emerging big-memory systems, the TLBs cease to provide the required performance benefits because they fail to cover the application's working set. The TLBs cannot scale with the cache hierarchies due to the hardware constraints and latency requirements, leading to the TLB scalability issue. Our goal is to solve the TLB scalability issue by designing a scalable address translation scheme without TLBs.
In this proposal, we discuss three existing works that try to address the TLB scalability issue. First, we show that the address translation can be deferred until accessing the memory by adopting virtual cache and intermediate address space. Performing the address translation within the cache hierarchies helps in removing TLBs from the system. Then we illustrate the benefit of transparent large pages in improving the TLB coverage. Finally, we discuss how exploiting application-level semantics can result in a scalable TLB-free address translation scheme and our follow-up works to enhance the scheme.
Background papers
1. DA Wood et al: An in-cache address translation mechanism
https://dl.acm.org/doi/abs/10.1145/17356.17398
2. L Zhang et al: Enigma: architectural and operating system support for reducing the impact of address translation
https://dl.acm.org/doi/abs/10.1145/1810085.1810109
3. S Gupta et al: Rebooting Virtual Memory with Midgard (accepted to appear at ISCA '21)
https://infoscience.epfl.ch/record/285466/files/midgard.pdf
Practical information
- General public
- Free
Organizer
- EDIC