ARMv8 : a next-generation vector architecture for HPC
In this talk we describe ARM's Scalable Vector Extension that significantly extends the vector processing capabilities associated with AArch64 (64-bit) execution in the ARM architecture, now and into the future. Several goals guided the design of SVE. First, the need to better address the compute requirements in domains such as high performance computing (HPC), data analytics and areas such as computer vision and machine learning, both now and into the future. Second, a desire for an architecture that scales across multiple implementations, allowing designers to choose the vector length most suitable for their power, performance and area targets. Last, a wish to minimize software development costs as the vector length scales by improving the reach of compiler auto-vectorization technologies.