Beyond ILP for FPGA-based HLS Tools
Event details
| Date | 22.07.2021 |
| Hour | 12:00 › 14:00 |
| Speaker | Ayatallah Elakhras |
| Category | Conferences - Seminars |
EDIC candidacy exam
exam president: Prof. Babak Falsafi
thesis advisor: Prof. Paolo Ienne
co-examiner: Prof. David Atienza
Abstract
Field Programmable Gate Arrays (FPGAs) are attractive
platforms for applications with high computational demands
and low energy consumption requirements. However, the
design effort for FPGA development remains high in comparison
to that for software development. High-level synthesis (HLS)
tools are meant to ease the process of FPGA development by
generating hardware designs from high level languages such
as C/C++. However, they do not always produce high quality
designs, especially for applications that can not be automatically
parallelized easily. In this report we study existing research work
aimed at improving different steps in the HLS process towards
better exploiting instruction-level parallelism (ILP) and easing
the design process. We conclude with a proposal for a research
direction we intend to take toward
Background papers
1) Title: Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests
Authors: Gai Liu, Mingxing Tan, Steve Dai, Ritchie Zhao, Zhiru Zhang
Link: https://ieeexplore.ieee.org/document/7842548
2) Title: A compiler Infrastructure for Accelerator Generators
Authors: Rachit Nigam, Samuel Thomas, Zhijing Li, Adrian Sampson
Link: https://dl.acm.org/doi/abs/10.1145/3445814.3446712
3) Title: Chronos: Efficient Speculative Parallelism for Accelerator
Authors: Maleen Abeydeera, Daniel Sanchez
Link: https://dl.acm.org/doi/abs/10.1145/3373376.3378454
exam president: Prof. Babak Falsafi
thesis advisor: Prof. Paolo Ienne
co-examiner: Prof. David Atienza
Abstract
Field Programmable Gate Arrays (FPGAs) are attractive
platforms for applications with high computational demands
and low energy consumption requirements. However, the
design effort for FPGA development remains high in comparison
to that for software development. High-level synthesis (HLS)
tools are meant to ease the process of FPGA development by
generating hardware designs from high level languages such
as C/C++. However, they do not always produce high quality
designs, especially for applications that can not be automatically
parallelized easily. In this report we study existing research work
aimed at improving different steps in the HLS process towards
better exploiting instruction-level parallelism (ILP) and easing
the design process. We conclude with a proposal for a research
direction we intend to take toward
Background papers
1) Title: Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests
Authors: Gai Liu, Mingxing Tan, Steve Dai, Ritchie Zhao, Zhiru Zhang
Link: https://ieeexplore.ieee.org/document/7842548
2) Title: A compiler Infrastructure for Accelerator Generators
Authors: Rachit Nigam, Samuel Thomas, Zhijing Li, Adrian Sampson
Link: https://dl.acm.org/doi/abs/10.1145/3445814.3446712
3) Title: Chronos: Efficient Speculative Parallelism for Accelerator
Authors: Maleen Abeydeera, Daniel Sanchez
Link: https://dl.acm.org/doi/abs/10.1145/3373376.3378454
Practical information
- General public
- Free