Beyond ILP for FPGA-based HLS Tools


Event details

Date and time 22.07.2021 12:0014:00  
Speaker Ayatallah Elakhras
Category Conferences - Seminars
EDIC candidacy exam
exam president: Prof. Babak Falsafi
thesis advisor: Prof. Paolo Ienne
co-examiner: Prof. David Atienza

Field Programmable Gate Arrays (FPGAs) are attractive
platforms for applications with high computational demands
and low energy consumption requirements. However, the
design effort for FPGA development remains high in comparison
to that for software development. High-level synthesis (HLS)
tools are meant to ease the process of FPGA development by
generating hardware designs from high level languages such
as C/C++. However, they do not always produce high quality
designs, especially for applications that can not be automatically
parallelized easily. In this report we study existing research work
aimed at improving different steps in the HLS process towards
better exploiting instruction-level parallelism (ILP) and easing
the design process. We conclude with a proposal for a research
direction we intend to take toward

Background papers
1)  Title: Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests
     Authors: Gai Liu, Mingxing Tan, Steve Dai, Ritchie Zhao, Zhiru Zhang

2)  Title: A compiler Infrastructure for Accelerator Generators
     Authors: Rachit Nigam, Samuel Thomas, Zhijing Li, Adrian Sampson

3)  Title: Chronos: Efficient Speculative Parallelism for Accelerator
     Authors: Maleen Abeydeera, Daniel Sanchez

Practical information

  • General public
  • Free


EDIC candidacy exam