Black Box Far-memory Aware Scalable Data Structures


Event details

Date 13.06.2023
Hour 10:3012:30
Speaker Yueyang Pan
Category Conferences - Seminars
EDIC candidacy exam
Exam president: Prof. James Larus
Thesis advisor: Prof. Sanidhya Kashyap
Co-examiner: Prof. George Candea

Memory Disaggregation architecture physically separates
CPU and memory into different components, usually
connected via high-speed network such as RDMA. The concept
of disaggregated memory was proposed more than a decade
ago. Recently, it has regained attention because of the memory
wall, the imbalanced resource utilization in the data centers and
the emergence of the new hardware. Different approaches have
been proposed to utilize disaggregated memory with different
efficiency and generality. This report first examines how Fastswap
utilizes transparently disaggregated memory via the kernel
swapping mechanism. Then it summarizes AIFM, a userspace
framework for data structure developers that tries to reduce
the overhead of the kernel mechanism. Finally it analyzes how
Sherman, a specialized B+Tree, achieves performance under
contended workloads. The report ends with the research proposal
to develop a general data structure development framework on
disaggregated memory.

Background papers
1. "Can Far Memory Improve Job Throughput?"
2. AIFM: High-Performance, Application-Integrated Far Memory
3. Sherman: A Write-Optimized Distributed B+Tree Index on Disaggregated Memory


Practical information

  • General public
  • Free


EDIC candidacy exam