Carbon Nanotube-FET and Interconnection Modeling for Analysis and Design of Emerging Nanoscale Integrated Circuits
Event details
| Date | 17.06.2011 |
| Hour | 10:00 |
| Speaker | Prof. Ashok Srivastava, Louisiana State University |
| Location |
ELA 2
|
| Category | Conferences - Seminars |
Carbon nanotubes, discovered in 1991 by Iijima of Japan, are one-dimensional graphene sheets rolled into a tubular structure of nanometer size. The one-dimensional carbon nanotube (CNT) has excellent electrical, mechanical and thermal properties which has made the CNT one of the promising materials for applications in nanoelectronics and micro/nano-systems. Their properties depend on the diameter and wrapping angle determined by the chiral vector which is characterized by the indices (n, m) of the graphene. Carbon nanotube field effect transistor (CNT-FET) has been identified as one of the promising candidates for future integrated circuits substituting shrinking CMOS integrated circuit technology at the end of the Moore’s law. Nanometer CMOS technology especially in 22 nm technology node and below is plagued due to performance degradation of conventional Cu/low-k dielectric as an interconnect material for gigascale integration. In search for novel technologies, no such material has aroused so much interest other than carbon nanomaterials since the discovery of carbon nanotube. In our recent work, we have modeled electronic transport in CNT-FETs, single-walled carbon nanotubes, multi-walled carbon nanotubes and single-walled carbon nanotube bundles as interconnects for on-chip integration. We have developed analytical models which can be used in Cadence/AMS mode simulations. In this seminar, I will present modeling equations and results describing the current transport in carbon nanotube field effect transistors and carbon nanotube interconnects for use in design of emerging logic devices similar to CMOS design style.
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Practical information
- General public
- Free
Contact
- Prof. Pascal Frossard