Dynamic Acceleration of Task-Parallel Algorithms on FPGAs
Event details
| Date | 02.06.2023 |
| Hour | 09:30 › 11:30 |
| Speaker | Mohamed Mahfouz Ahmed Kotb Shahawy |
| Category | Conferences - Seminars |
EDIC candidacy exam
Exam president: Prof. Edouard Bugnion
Thesis advisor: Prof. Paolo Ienne
Co-examiner: Prof. Rachid Guerraoui
Abstract
Field Programmable Gate Arrays (FPGAs) witnessed multiple leaps in their programmability through the development of High-Level Synthesis (HLS) tools that enabled more accessibility to non-expert users of FPGAs. The current HLS tools exploit specific types of parallelism in the produced circuits, like Instruction Level Parallelism (ILP). Support of Task-Level Parallelism (TLP) in HLS has been recently explored on FPGAs with systems like ParallelXL, TAPAS, and TaPaSCo. This report examines TLP from a software side through the Cilk runtime system. Second, it analyzes ParallelXL, an effort to bring TLP support to FPGAs using the programming model from Cilk. Then, it investigates a recent graph cycle enumeration algorithm that uses software TLP as a possible candidate for FPGA acceleration. Finally, the report concludes with a research proposal that identifies the line of research to support TLP for FPGAs.
Background papers
Exam president: Prof. Edouard Bugnion
Thesis advisor: Prof. Paolo Ienne
Co-examiner: Prof. Rachid Guerraoui
Abstract
Field Programmable Gate Arrays (FPGAs) witnessed multiple leaps in their programmability through the development of High-Level Synthesis (HLS) tools that enabled more accessibility to non-expert users of FPGAs. The current HLS tools exploit specific types of parallelism in the produced circuits, like Instruction Level Parallelism (ILP). Support of Task-Level Parallelism (TLP) in HLS has been recently explored on FPGAs with systems like ParallelXL, TAPAS, and TaPaSCo. This report examines TLP from a software side through the Cilk runtime system. Second, it analyzes ParallelXL, an effort to bring TLP support to FPGAs using the programming model from Cilk. Then, it investigates a recent graph cycle enumeration algorithm that uses software TLP as a possible candidate for FPGA acceleration. Finally, the report concludes with a research proposal that identifies the line of research to support TLP for FPGAs.
Background papers
- An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware (https://ieeexplore.ieee.org/document/8574531)
- Cilk: an efficient multithreaded runtime system (https://dl.acm.org/doi/10.1145/209937.209958)
- Scalable Fine-Grained Parallel Cycle Enumeration Algorithms (https://dl.acm.org/doi/10.1145/3490148.3538585)
Practical information
- General public
- Free