Elastic Coarse Grained Reconfigurable Array
Event details
| Date | 29.06.2022 |
| Hour | 10:00 › 12:00 |
| Speaker | Louis Coulon |
| Location | |
| Category | Conferences - Seminars |
EDIC candidacy exam
Exam president: Prof. Martin Odersky
Thesis advisor: Prof. Paolo Ienne
Thesis co-advisor: Dr. Mirjana Stojilovic
Co-examiner: Prof. Babak Falsafi
Abstract
With the end of Moore's law and Dennard scaling, there is an increasing need for hardware specialization to meet the computational requirements of applications and run them with improved energy efficiency. Programmable devices, such as Field Programmable Gate Arrays (FPGAs), are good candidates to meet such needs as they allow designers to customize the hardware for each application. While programming FPGAs using Hardware Description Languages such as VHDL or Verilog allows one to achieve efficient implementations, it requires in-depth hardware knowledge and limits the utilization of FPGAs. As a result, to widen the adoption of FPGAs, other programming paradigms such as High-Level Synthesis(HLS), which compiles high-level programs to circuits, have been developed. However, HLS-generated circuits might lead to, surprisingly, moderately efficient implementations. Indeed, FPGAs are bit-level devices based on LUTs, while programs are usually word-level, making them a poor fit for such an architecture. Another type of architectures, Coarse Grained Reconfigurable Arrays (CGRAs), could be more suitable but are also a poor fit since they are generally small and only support flavors of modulo scheduling. This poor fit calls for another type of architecture. During the presentation, we will first go over recent work on dynamically scheduled high-level synthesis, which brings out-of-order execution to circuits. Then, we will review some of the main design directions followed so far in CGRA architecture. Finally, we will underline the missing pieces of current CGRA designs and the future work directions we are investigating.
Background papers
[1] https://ieeexplore.ieee.org/document/9439439
[2] https://ieeexplore.ieee.org/document/1611540
[3] https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1188678
Exam president: Prof. Martin Odersky
Thesis advisor: Prof. Paolo Ienne
Thesis co-advisor: Dr. Mirjana Stojilovic
Co-examiner: Prof. Babak Falsafi
Abstract
With the end of Moore's law and Dennard scaling, there is an increasing need for hardware specialization to meet the computational requirements of applications and run them with improved energy efficiency. Programmable devices, such as Field Programmable Gate Arrays (FPGAs), are good candidates to meet such needs as they allow designers to customize the hardware for each application. While programming FPGAs using Hardware Description Languages such as VHDL or Verilog allows one to achieve efficient implementations, it requires in-depth hardware knowledge and limits the utilization of FPGAs. As a result, to widen the adoption of FPGAs, other programming paradigms such as High-Level Synthesis(HLS), which compiles high-level programs to circuits, have been developed. However, HLS-generated circuits might lead to, surprisingly, moderately efficient implementations. Indeed, FPGAs are bit-level devices based on LUTs, while programs are usually word-level, making them a poor fit for such an architecture. Another type of architectures, Coarse Grained Reconfigurable Arrays (CGRAs), could be more suitable but are also a poor fit since they are generally small and only support flavors of modulo scheduling. This poor fit calls for another type of architecture. During the presentation, we will first go over recent work on dynamically scheduled high-level synthesis, which brings out-of-order execution to circuits. Then, we will review some of the main design directions followed so far in CGRA architecture. Finally, we will underline the missing pieces of current CGRA designs and the future work directions we are investigating.
Background papers
[1] https://ieeexplore.ieee.org/document/9439439
[2] https://ieeexplore.ieee.org/document/1611540
[3] https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1188678
Practical information
- General public
- Free