Exploiting Bandwidth in 3D-Integrated Chip Multiprocessors
Event details
| Date | 25.06.2010 |
| Hour | 12:30 |
| Speaker | Mr Ðorde Jevdic |
| Location | |
| Category | Conferences - Seminars |
EDIC Candidacy Exam:
Exam president: Prof. Giovanni De Micheli
Thesis director: Prof. Babak Falsafi
Co-examiner: Prof. Dejan Kostic
Research Proposal
3D-Stacked Memory Architectures for Multi-core Processors by G. H. Loh
An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth. HPCA 2010 by Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, and Hsien-Hsin S. Lee.
Bridging the Processor-Memory Performance Gap with 3D IC Technology. IEEE Design & Test of Computers, 22(6):556.564, 2005 by C. Liu, I. Ganusov, M. Burtscher, and S. Tiwari
Exam president: Prof. Giovanni De Micheli
Thesis director: Prof. Babak Falsafi
Co-examiner: Prof. Dejan Kostic
Research Proposal
3D-Stacked Memory Architectures for Multi-core Processors by G. H. Loh
An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth. HPCA 2010 by Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, and Hsien-Hsin S. Lee.
Bridging the Processor-Memory Performance Gap with 3D IC Technology. IEEE Design & Test of Computers, 22(6):556.564, 2005 by C. Liu, I. Ganusov, M. Burtscher, and S. Tiwari
Practical information
- General public
- Free
Contact
- Evelyn Duperrex