FPGA-Accelerated Performance Model for Architecture Research

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Event details

Date 01.07.2021
Hour 15:0017:00
Speaker Shanqing Lin
Category Conferences - Seminars
EDIC candidacy exam
exam president: Prof. James Larus
thesis advisor: Prof. Babak Falsafi
co-examiner: Prof. Paolo Ienne

Abstract
Microarchitecture simulators are essential tools for system research, and software simulators suffer from their limited performance due to the finer parallelism in the model's implementation. FPGAs are naturally applied to accelerate simulation to gain more throughput due to their capacity to exploit fine-grained parallelism. This report will examine three paradigms of FPGA-accelerated simulators and their evolution on performance and accuracy. Two directions, including scale-out simulation and domain-specific representations, are also proposed to improve performance, accuracy, and usability.

Background papers
UT-FAST: https://ieeexplore.ieee.org/abstract/document/4408260
Ramp Gold: https://dl.acm.org/doi/abs/10.1145/1815961.1815999
HASim: https://ieeexplore.ieee.org/abstract/document/5749747
 

Practical information

  • General public
  • Free

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EDIC candidacy exam

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