From Variability-Tolerance to Approximate Computing
Event details
| Date | 03.03.2015 |
| Hour | 10:00 › 11:00 |
| Speaker |
Dr. Abbas Rahimi, Department of Computer Science and Engineering, University of California, San Diego Abbas Rahimi is currently a fifth year Ph.D. candidate in the Department of Computer Science and Engineering at the University of California, San Diego. He is working with Professor Rajesh Gupta and Professor Luca Benini. Since June 2010, he has also been with the Microelectronic Group at the University of Bologna. His research interests are in the massively parallel integrated architectures, approximate computing, resilient system design, design for robustness, embedded systems, and on-chip interconnections. In these areas, he has published more than 20 papers in top tier conferences and journals. Mr. Rahimi received the Best Paper Candidate at 50th IEEE/ACM Design Automation Conference. He received the B.S. degree in computer engineering from the School of Electrical and Computer Engineering at the University of Tehran, in March 2010. |
| Location | |
| Category | Conferences - Seminars |
Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in modern microelectronic manufacturing processes with geometries in nanometer scales. These variations cause timing errors in computing systems that are typically avoided by ultra-conservative multi-corner design margins. Keeping the focus on timing errors, we investigated separate methodological approaches to predict-and-prevent, to detect-and-correct, and finally, to ignore timing errors; we evaluated their implications on cost, performance and quality of the output results. Further, we devise an arsenal of approximate computing and memoization-based optimizations techniques for improving cost and scale of these approaches in massively parallel computing units, such as those found in GP-GPUs and other clustered many-core accelerators. The result was a framework for cross-layer (i.e., across software stack) and hybrid (i.e., across hardware and software) resiliency. This enabled us to combine error correction and error ignorance to devise a method for approximate error correction across the hardware/software interface via memoization. That is, ensuring safety of error-tolerance through a set of rules verified by a combination of design-time and runtime constraints. Together with the use of a memristive memory block, spatial and temporal memoization was shown to significantly reduce the cost of resiliency and enhance the range of variability-induced timing errors that can be recovered at very low cost.
Practical information
- General public
- Free
Organizer
- Institute of Electrical Engineering