Global Circuit Restructuring for Efficient Hardware Synthesis
Event details
| Date | 07.09.2012 |
| Hour | 13:30 |
| Speaker | Ms Ana Petkovska |
| Location | |
| Category | Conferences - Seminars |
EDIC Candidacy Exam:
Exam president: Prof. De Micheli
Thesis director: Prof. Paolo Ienne
Co-examiner: Prof. Aleksander Madry
Research Proposal
Iterative Layering: Optimizing Arithmetic Circuits by Structuring the Information Flow by A. K. Verma, P. Brisk, and P. Ienne.
Interpolation and SAT-based Model Checking. by K. L. McMillan
Mapping into LUT structures by S. Ray, A. Mishchenko, N. Een, R. Brayton, S. Jang, and C. Chen.
Exam president: Prof. De Micheli
Thesis director: Prof. Paolo Ienne
Co-examiner: Prof. Aleksander Madry
Research Proposal
Iterative Layering: Optimizing Arithmetic Circuits by Structuring the Information Flow by A. K. Verma, P. Brisk, and P. Ienne.
Interpolation and SAT-based Model Checking. by K. L. McMillan
Mapping into LUT structures by S. Ray, A. Mishchenko, N. Een, R. Brayton, S. Jang, and C. Chen.
Practical information
- General public
- Free
Contact
- Evelyn Duperrex