High Density On-Chip Memories for Future Processors
Event details
| Date | 28.03.2011 |
| Hour | 15:00 |
| Speaker | Prof. Kaushik ROY, Electrical and Computer Engineering Faculty, Purdue University |
| Location |
ELA 2
|
| Category | Conferences - Seminars |
Scaling of technology has adverse effects on stability of on-chip memories.
Due to increased leakage current and parameter variations and the need for minimal sized transistors for high density, the standard 6T SRAM cells show high failure rate at low supply voltages. In this talk I will explore different memory design options and technologies for future on-chip caches. In particular, I will focus on design and optimization of spin-transfer torque magnetic memories (using spin as a state variable) which has the possibility of replacing high level on-chip caches/main-memory in future processors. Finally (time permitting), I will consider the possibilities of logic design using spin as a state variable.
Practical information
- General public
- Free
Contact
- Prof. Andreas Burg