IEM Distinguished Lecturers Seminar: Error-correcting codes for hyper-speed memory and data storage: from theory to practice
***Coffee and cookies will be served at 13:00 in the hall of BM 5202***
Abstract
Reliable hyper-speed and large-scale memory/storage systems are the backbone of data-centric computing, high-performance cloud computing, big data analytics, and many other pervasive applications. Error-correcting codes achieving terabit/s throughput with excellent correction capability are essential to unleashing the potential of next-generation memories. To enable the continued scaling of distributed storage, failure recovery schemes that have short latency and low penalty on the network bandwidth are necessary. Many of the error/erasure-correcting coding schemes for addressing these requirements are based on nesting, splitting, and coupling Reed-Solomon or BCH codes. This talk focuses on algorithmic reformulations and architectural modifications that translate these advanced coding schemes to efficient implementations. The optimizations of code construction, encoding and decoding algorithms, and the hardware implementation are integrated to eliminate the hardware bottlenecks and achieve unprecedented improvements on throughput, latency, and silicon area requirement.
Bio
Xinmiao Zhang received her Ph.D. degree from the University of Minnesota in 2005. She is currently a Professor at The Ohio State University. Dr. Zhang's research spans the areas of digital storage and communications, hardware architecture design, cryptography, hardware security, and signal processing. She is a recipient of the NSF CAREER Award in 2009, Lumley Research Award at The Ohio State University 2022, Best Paper Award at International SanDisk Technology Conference 2016, and Best Paper Award at ACM Great Lakes Symposium on VLSI 2004. She authored the book “VLSI Architectures for Modern Error-Correcting Codes” (CRC Press, 2015). She was the Vice President-Technical Activities of the IEEE Circuits and Systems Society (CASS) for the 2022-2023 term and the Chair of the Data Storage Technical Committee (DSTC) of the IEEE Communications Society for the 2021-2022 term. She served on the technical program and organization committees of many conferences, including ISCAS, SiPS, ICC, GLOBECOM, GlobalSIP, and GLSVLSI. She is the Associate Editor-in-Chief of the IEEE Transactions on Circuits and Systems-I 2024-2025.
Abstract
Reliable hyper-speed and large-scale memory/storage systems are the backbone of data-centric computing, high-performance cloud computing, big data analytics, and many other pervasive applications. Error-correcting codes achieving terabit/s throughput with excellent correction capability are essential to unleashing the potential of next-generation memories. To enable the continued scaling of distributed storage, failure recovery schemes that have short latency and low penalty on the network bandwidth are necessary. Many of the error/erasure-correcting coding schemes for addressing these requirements are based on nesting, splitting, and coupling Reed-Solomon or BCH codes. This talk focuses on algorithmic reformulations and architectural modifications that translate these advanced coding schemes to efficient implementations. The optimizations of code construction, encoding and decoding algorithms, and the hardware implementation are integrated to eliminate the hardware bottlenecks and achieve unprecedented improvements on throughput, latency, and silicon area requirement.
Bio
Xinmiao Zhang received her Ph.D. degree from the University of Minnesota in 2005. She is currently a Professor at The Ohio State University. Dr. Zhang's research spans the areas of digital storage and communications, hardware architecture design, cryptography, hardware security, and signal processing. She is a recipient of the NSF CAREER Award in 2009, Lumley Research Award at The Ohio State University 2022, Best Paper Award at International SanDisk Technology Conference 2016, and Best Paper Award at ACM Great Lakes Symposium on VLSI 2004. She authored the book “VLSI Architectures for Modern Error-Correcting Codes” (CRC Press, 2015). She was the Vice President-Technical Activities of the IEEE Circuits and Systems Society (CASS) for the 2022-2023 term and the Chair of the Data Storage Technical Committee (DSTC) of the IEEE Communications Society for the 2021-2022 term. She served on the technical program and organization committees of many conferences, including ISCAS, SiPS, ICC, GLOBECOM, GlobalSIP, and GLSVLSI. She is the Associate Editor-in-Chief of the IEEE Transactions on Circuits and Systems-I 2024-2025.
Practical information
- General public
- Free