IEM Seminar: Chiplets, a Rose with a Different Name
Event details
| Date | 10.05.2024 |
| Hour | 11:00 › 12:00 |
| Speaker | Marco Casale-Rossi, Synopsys, Inc. |
| Location | |
| Category | Conferences - Seminars |
| Event Language | English |
Extended Abstract
For as long as I have been in the industry, engineers have striven to foster the integration among the most disparate functions of an electronic system. The name of this effort has changed overtime: Multi-Chip-Module (MCM), System-on-Chip (SoC), System-in-Package (SiP), 2.5D-, 3D-, and 5.5D-IC. Chiplet is the most recent, fashionable name of this unstoppable attempt to push the limits of integration a bit further. However, after the Bard, “which we call a rose, by any other name would smell as sweet” (Romeo and Juliet, Act II, Scene II).
The pendulum has periodically oscillated between front-end – lithography – monolithic integration, and back-end – assembly and packaging – discrete integration. The objectives of this effort have always been to improve raw performance, reduce latency, increase bandwidth, reduce the amount of costly silicon real estate, and slash power consumption.
In this talk, I will take a contrarian view, illustrate different examples of integration, and point-out how chiplets are one possibility to push integration forward, but not the only possibility. I will illustrate how the same problem can be solved with, or without chiplets.
Finally, I will illustrate chiplets geopolitical impact. While wafer fabs are currently located in Taiwan, South Korea, and in the U.S., assembly and packaging fabs are located in Singapore, Malaysia, and PRC. The oscillation of the pendulum from front-end to back-end integration may also [irreparably? permanently?] alter the equilibrium of the supply chain of the semiconductor industry, the heart of the electronic industry.
Speakers Bio
Marco Casale-Rossi has joined Synopsys in 2005, after 20 years at STMicroelectronics Central R&D and ASIC R&D departments, where he has participated in the development and deployment of one of the first “industrial” ASIC implementation EDA solutions. Marco’s most recent responsibility at ST was the management of the technology collaborations with the EDA partners. In the last 19 years, Marco has contributed building Synopsys vision of the design and technology roadmap, most recently as a member of the Office of the CEO.
For as long as I have been in the industry, engineers have striven to foster the integration among the most disparate functions of an electronic system. The name of this effort has changed overtime: Multi-Chip-Module (MCM), System-on-Chip (SoC), System-in-Package (SiP), 2.5D-, 3D-, and 5.5D-IC. Chiplet is the most recent, fashionable name of this unstoppable attempt to push the limits of integration a bit further. However, after the Bard, “which we call a rose, by any other name would smell as sweet” (Romeo and Juliet, Act II, Scene II).
The pendulum has periodically oscillated between front-end – lithography – monolithic integration, and back-end – assembly and packaging – discrete integration. The objectives of this effort have always been to improve raw performance, reduce latency, increase bandwidth, reduce the amount of costly silicon real estate, and slash power consumption.
In this talk, I will take a contrarian view, illustrate different examples of integration, and point-out how chiplets are one possibility to push integration forward, but not the only possibility. I will illustrate how the same problem can be solved with, or without chiplets.
Finally, I will illustrate chiplets geopolitical impact. While wafer fabs are currently located in Taiwan, South Korea, and in the U.S., assembly and packaging fabs are located in Singapore, Malaysia, and PRC. The oscillation of the pendulum from front-end to back-end integration may also [irreparably? permanently?] alter the equilibrium of the supply chain of the semiconductor industry, the heart of the electronic industry.
Speakers Bio
Marco Casale-Rossi has joined Synopsys in 2005, after 20 years at STMicroelectronics Central R&D and ASIC R&D departments, where he has participated in the development and deployment of one of the first “industrial” ASIC implementation EDA solutions. Marco’s most recent responsibility at ST was the management of the technology collaborations with the EDA partners. In the last 19 years, Marco has contributed building Synopsys vision of the design and technology roadmap, most recently as a member of the Office of the CEO.
Practical information
- General public
- Free
Contact
- Giovanni De Micheli