IEM Seminar Series: In-memory Computing – Fundamentals, Current Trends, and Future Directions
Event details
| Date | 24.03.2023 |
| Hour | 11:15 › 12:00 |
| Speaker |
Prof. Naresh R. Shanbhag, Jack Kilby Professor of Electrical and Computer Engineering University of Illinois, Urbana-Champaign, US |
| Location | Online |
| Category | Conferences - Seminars |
| Event Language | English |
Abstract
In-memory computing (IMC) has emerged as an attractive complement to digital accelerators for enhancing the energy efficiency of machine learning tasks. IMC addresses the energy and latency costs of memory accesses dominating AI workloads by transforming the conventional memory accesses into one that computes functions of data in the memory core in an analog/mixed-signal manner. As a result, IMC chips have demonstrated > 100X reduction in the energy-delay product over equivalent von Neumann architectures at iso-accuracy. IMCs also exhibit a fundamental energy vs. SNR trade-off that designers need to exploit to enhance energy efficiency while meeting task-level accuracy requirements. Since the publication of the concept in our ICASSP 2014 paper, IMC design has become an active area of research in the machine learning integrated circuits and architecture communities. This talk will describe IMC design principles, review current trends based on our recent efforts in extensive benchmarking (https://github.com/naresh-shanbhag/UIUC-IMC-Benchmarking), and identify future opportunities and challenges in deploying IMCs at scale in emerging applications.
Bio
Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. He received his Ph.D. degree from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill where he led the design of high-speed transceiver chipsets for very high-speed digital subscriber line (VDSL), before joining the University of Illinois at Urbana- Champaign in August 1995. He has held visiting faculty appointments at the National Taiwan University (Aug.-Dec. 2007) and Stanford University (Aug.-Dec. 2014). His research focuses on the design of energy-efficient systems for machine learning, communications, and signal processing, spanning algorithms, VLSI architectures, and integrated circuits. He has more than 200 publications in this area, holds thirteen US patents, and is a co-author of two books and multiple book chapters (see https://shanbhag.ece.illinois.edu/ for details).
Dr. Shanbhag received the 2018 SIA/SRC University Researcher Award, became an IEEE Fellow in 2006, received the 2010 Richard Newton GSRC Industrial Impact Award, the IEEE Circuits and Systems Society Distinguished Lecturership in 1997, the National Science Foundation CAREER Award in 1996, and multiple best paper awards. In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of the Intersymbol Communications, Inc., which introduced mixed-signal ICs for electronic dispersion compensation of OC-192 optical links, and became a part of Finisar Corporation in 2007. From 2013-17, he was the founding Director of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi- university center funded by DARPA and SRC under the STARnet program. He is currently on the leadership teams of the JUMP 2.0 DARPA and SRC funded Centers for Ubiquitous Connectivity (CUbiC) and Codesign of Cognitive Systems (CoCoSys), and the NSF-industry funded Center for Advanced Semiconductor Chips for Accelerated Performance (ASAP).
In-memory computing (IMC) has emerged as an attractive complement to digital accelerators for enhancing the energy efficiency of machine learning tasks. IMC addresses the energy and latency costs of memory accesses dominating AI workloads by transforming the conventional memory accesses into one that computes functions of data in the memory core in an analog/mixed-signal manner. As a result, IMC chips have demonstrated > 100X reduction in the energy-delay product over equivalent von Neumann architectures at iso-accuracy. IMCs also exhibit a fundamental energy vs. SNR trade-off that designers need to exploit to enhance energy efficiency while meeting task-level accuracy requirements. Since the publication of the concept in our ICASSP 2014 paper, IMC design has become an active area of research in the machine learning integrated circuits and architecture communities. This talk will describe IMC design principles, review current trends based on our recent efforts in extensive benchmarking (https://github.com/naresh-shanbhag/UIUC-IMC-Benchmarking), and identify future opportunities and challenges in deploying IMCs at scale in emerging applications.
Bio
Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. He received his Ph.D. degree from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill where he led the design of high-speed transceiver chipsets for very high-speed digital subscriber line (VDSL), before joining the University of Illinois at Urbana- Champaign in August 1995. He has held visiting faculty appointments at the National Taiwan University (Aug.-Dec. 2007) and Stanford University (Aug.-Dec. 2014). His research focuses on the design of energy-efficient systems for machine learning, communications, and signal processing, spanning algorithms, VLSI architectures, and integrated circuits. He has more than 200 publications in this area, holds thirteen US patents, and is a co-author of two books and multiple book chapters (see https://shanbhag.ece.illinois.edu/ for details).
Dr. Shanbhag received the 2018 SIA/SRC University Researcher Award, became an IEEE Fellow in 2006, received the 2010 Richard Newton GSRC Industrial Impact Award, the IEEE Circuits and Systems Society Distinguished Lecturership in 1997, the National Science Foundation CAREER Award in 1996, and multiple best paper awards. In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of the Intersymbol Communications, Inc., which introduced mixed-signal ICs for electronic dispersion compensation of OC-192 optical links, and became a part of Finisar Corporation in 2007. From 2013-17, he was the founding Director of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi- university center funded by DARPA and SRC under the STARnet program. He is currently on the leadership teams of the JUMP 2.0 DARPA and SRC funded Centers for Ubiquitous Connectivity (CUbiC) and Codesign of Cognitive Systems (CoCoSys), and the NSF-industry funded Center for Advanced Semiconductor Chips for Accelerated Performance (ASAP).
Practical information
- General public
- Free