Improving Performance with Neural Branch Prediction
Event details
| Date | 26.08.2010 |
| Hour | 14:00 |
| Speaker | Prof. Daniel Ángel Jiménez |
| Location | |
| Category | Conferences - Seminars |
Microprocessors achieve good performance by executing many instructions in parallel. A bottleneck is introduced when a program makes a decision using a conditional branch instruction since the processor cannot execute more instructions until it knows the outcome of the decision. To reduce this bottleneck, microprocessors use branch predictors to speculatively fetch and execute instructions beyond branches. The penalty of an incorrect prediction is substantial, so improving branch predictor accuracy has the potential to significantly improve overall performance. Current branch predictors use ad-hoc tables of counters to learn branch behavior from past history. Prof. Jiménez presents a highly successful line of research into improving branch predictor accuracy using a different aproach: neural learning. He introduces the concept of neural branch prediction, shows how to build a feasible neural branch predictor with low latency, and presents a technique to overcome the traditional limitations of simple neural learning. Neural branch predictors are among the most accurate in the literature today.
Links
Practical information
- General public
- Free
Contact
- Stéphanie Baillargues