Logic design and technology mapping for superconducting circuits
Event details
| Date | 28.06.2021 |
| Hour | 15:30 › 17:30 |
| Speaker | Alessandro Tempia Calvino |
| Category | Conferences - Seminars |
EDIC candidacy exam
exam president: Prof. Viktor Kuncak
thesis advisor: Prof. Giovanni De Micheli
co-examiner: Prof. Catherine Dehollain
expert: Dr. Heinz Riener
Abstract
Superconducting electronics (SCE) gained recent interest by proposing scalable and power-efficient solutions to overcome the limitations and challenges of CMOS technology in reducing energy consumption. SCE logic such as rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) differs from standard CMOS electronics in several aspects introducing new constraints that electronic design automation (EDA) tools have to support. In particular, logic gates are clocked elements, data is required to be available in specific time-frames, and branching elements are necessary to drive multiple cells. State-of-the-art logic synthesis tools describe a circuit using technology-independent representations, apply logic optimizations, and map into a technology-dependent representation. In this proposal, the transformation of a technology-independent logic circuit to an optimized technology-dependent one is reviewed. First, the fundamentals of technology mapping and how to obtain a good technology-independent graph structure suitable for mapping are introduced. Then, a remapping technique to further improve a circuit accounting for technology constraints is presented. Next, an architecture for single-flux-quantum (SFQ) circuits is analyzed. Finally, possible research directions focusing on logic synthesis techniques for SCE are proposed.
Background papers
1) "Reducing structural bias in technology mapping”, by S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang and T. Kam
https://ieeexplore.ieee.org/document/1560122
2) “Iterative remapping for logic circuits", by L. Benini, P. Vuillod and G. De Micheli
https://ieeexplore.ieee.org/document/728916
3) “An Efficient Pipelined Architecture for Superconducting Single Flux Quantum Logic Circuits Utilizing Dual Clocks", by G. Pasandi and M. Pedram
https://ieeexplore.ieee.org/document/8910442
exam president: Prof. Viktor Kuncak
thesis advisor: Prof. Giovanni De Micheli
co-examiner: Prof. Catherine Dehollain
expert: Dr. Heinz Riener
Abstract
Superconducting electronics (SCE) gained recent interest by proposing scalable and power-efficient solutions to overcome the limitations and challenges of CMOS technology in reducing energy consumption. SCE logic such as rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) differs from standard CMOS electronics in several aspects introducing new constraints that electronic design automation (EDA) tools have to support. In particular, logic gates are clocked elements, data is required to be available in specific time-frames, and branching elements are necessary to drive multiple cells. State-of-the-art logic synthesis tools describe a circuit using technology-independent representations, apply logic optimizations, and map into a technology-dependent representation. In this proposal, the transformation of a technology-independent logic circuit to an optimized technology-dependent one is reviewed. First, the fundamentals of technology mapping and how to obtain a good technology-independent graph structure suitable for mapping are introduced. Then, a remapping technique to further improve a circuit accounting for technology constraints is presented. Next, an architecture for single-flux-quantum (SFQ) circuits is analyzed. Finally, possible research directions focusing on logic synthesis techniques for SCE are proposed.
Background papers
1) "Reducing structural bias in technology mapping”, by S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang and T. Kam
https://ieeexplore.ieee.org/document/1560122
2) “Iterative remapping for logic circuits", by L. Benini, P. Vuillod and G. De Micheli
https://ieeexplore.ieee.org/document/728916
3) “An Efficient Pipelined Architecture for Superconducting Single Flux Quantum Logic Circuits Utilizing Dual Clocks", by G. Pasandi and M. Pedram
https://ieeexplore.ieee.org/document/8910442
Practical information
- General public
- Free
Organizer
- EDIC