Logic Synthesis for High-Performance Hardware
Event details
| Date | 16.06.2022 |
| Hour | 11:00 › 13:00 |
| Speaker | Andrea Costamagna |
| Location | |
| Category | Conferences - Seminars |
EDIC candidacy exam
Exam president: Prof. Andreas Burg
Thesis advisor: Prof. Giovanni de Micheli
Co-examiner: Prof. Paolo Ienne
Abstract
Logic synthesis is a design phase that optimizes abstract circuit representations and maps them to technology. Combined with Dennard scaling, this field of research has been the driving force behind the Digital Revolution, enabling the design of very large-scale integrated circuits. With CMOS devices at the nanometer range, scaling transistors down can no longer guarantee a financially and energetically sustainable exponential growth in computing power. Hence, the paramount need for speed improvements requires the development of more efficient synthesis paradigms. Technology-aware logic synthesis is a recent trend in the industry targeting the introduction of technological information early in the design flow. This approach yields improved Quality of Results, induced by a better correlation between RTL synthesis and physical implementation. A recent breakthrough in technology-aware delay synthesis enabled the optimization of circuit designs up to local optimality [1]. Further advancements in the field require extending optimality toward less-local circuit portions. The proposed approach for achieving this goal involves combining the results in two branches of research. On the one hand, there are technology-oriented synthesis heuristics. The presented symmetry-detection-based synthesis technique is an example [2]. On the other hand, there are flexible data structures for Boolean reasoning [3]. This proposal reviews the mentioned background [1]-[3] and discusses a strategy to advance the research toward higher-performance hardware.
Background papers
Exam president: Prof. Andreas Burg
Thesis advisor: Prof. Giovanni de Micheli
Co-examiner: Prof. Paolo Ienne
Abstract
Logic synthesis is a design phase that optimizes abstract circuit representations and maps them to technology. Combined with Dennard scaling, this field of research has been the driving force behind the Digital Revolution, enabling the design of very large-scale integrated circuits. With CMOS devices at the nanometer range, scaling transistors down can no longer guarantee a financially and energetically sustainable exponential growth in computing power. Hence, the paramount need for speed improvements requires the development of more efficient synthesis paradigms. Technology-aware logic synthesis is a recent trend in the industry targeting the introduction of technological information early in the design flow. This approach yields improved Quality of Results, induced by a better correlation between RTL synthesis and physical implementation. A recent breakthrough in technology-aware delay synthesis enabled the optimization of circuit designs up to local optimality [1]. Further advancements in the field require extending optimality toward less-local circuit portions. The proposed approach for achieving this goal involves combining the results in two branches of research. On the one hand, there are technology-oriented synthesis heuristics. The presented symmetry-detection-based synthesis technique is an example [2]. On the other hand, there are flexible data structures for Boolean reasoning [3]. This proposal reviews the mentioned background [1]-[3] and discusses a strategy to advance the research toward higher-performance hardware.
Background papers
- Mishchenko, Alan, et al. "FRAIGs: A unifying representation for logic synthesis and verification". ERL Technical Report, 2005. https://ptolemy.berkeley.edu/projects/embedded/mvsis/doc/2004/fraigs.pdf
- Amarú, Luca, et al. "Enabling exact delay synthesis." 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2017. https://ieeexplore.ieee.org/abstract/document/8203799
- Edwards, C. R., & Hurst, S. L. (1978). "A digital synthesis procedure under function symmetries and mapping methods". IEEE Transactions on Computers, 27(11), 985-997. https://ieeexplore.ieee.org/abstract/document/1674988
Practical information
- General public
- Free