Nanowires from 1D to 3D devices and memories
Event details
| Date | 24.06.2010 |
| Hour | 15:00 |
| Speaker | Thomas Ernst, CEA-LETI, Grenoble, France |
| Location |
INM 202
|
| Category | Conferences - Seminars |
3D CMOS nanowire matrices and 2D thin film technologies recently developed, enable not only sub-22nm CMOS device scaling, but also ultimate co-integration of novel functionalities. For CMOS scaling, Silicon-On-Insulator (SOI) or innovative Silicon-On-Nothing (SON) based 3D nanowires are proposed with common or independent gates. Ultra-low static consumption, as well as high driving current were achieved thanks to 3D stacked Gate-All-Around (GAA) nanowire channels. The top-down nanowire techniques also open up new opportunities for hybridizing CMOS with novel functionalities such as 3D memories, nano-oscillators and bio nano-sensors.
Practical information
- General public
- Free
Contact
- Anil Leblebici