On Fixed FPGA Interconnect

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Event details

Date 05.07.2018
Hour 14:3016:30
Speaker Stefan Nikolic
Location
Category Conferences - Seminars
EDIC candidacy exam
Exam president: Prof. Giovanni De Micheli
Thesis advisor: Prof. Paolo Ienne
Co-examiner: Prof. Michael Kapralov

Abstract
This report presents three papers related to the problem of reducing FPGA interconnect flexibility by introduction of fixed connections. One of them provides motivation for such endeavor, while the others address scalability issues in the context of CAD tools and design space exploration. Finally, a brief discussion on future work in this area is included.

Background papers
Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization), A. DeHon, in Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays (FPGA '99), ACM, New York, NY, USA, 69-78.
Global network alignment using multiscale spectral signatures,  R. Patro and C. Kingsford, in Bioinformatics, vol. 28, no. 23 (December 2012), 3105-3114.
Polynomial time analysis of toroidal periodic graphs, F. Höfting and E. Wanke, in Abiteboul S., Shamir E. (eds) Automata, Languages and Programming, ICALP 1994, Lecture Notes in Computer Science, vol 820, Springer, Berlin, Heidelberg

Practical information

  • General public
  • Free

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EDIC candidacy exam

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