Performance Interface for Hardware Accelerators
Event details
| Date | 07.09.2023 |
| Hour | 09:30 › 11:30 |
| Speaker | Jiacheng Ma |
| Location | |
| Category | Conferences - Seminars |
EDIC candidacy exam
Exam president: Prof. Babak Falsafi
Thesis advisor: Prof. George Candea
Co-examiner: Prof. Thomas Bourgeat
Abstract
Propose performance interface for hardware circuit (RTL level) and querying latency or verifying performance properties through proposed performance interface.
Hardware accelerators should come with performance interfacesâinterfaces that provide usable information about the acceleratorâs performance behavior just like semantic interfaces do for functionality. Since accelerators aimed at improving system performance, their performance behavior should be clearly stated to the users, through a performance interface.
A performance interface intends to abstract away implementation details that do not pertain to performance. A performance interface should be systematically derived that leverage common constructs, such that further tools can be invented to
analyze performance and verify performance properties of the hardware circuit automatically through performance interface.
Background papers
Exam president: Prof. Babak Falsafi
Thesis advisor: Prof. George Candea
Co-examiner: Prof. Thomas Bourgeat
Abstract
Propose performance interface for hardware circuit (RTL level) and querying latency or verifying performance properties through proposed performance interface.
Hardware accelerators should come with performance interfacesâinterfaces that provide usable information about the acceleratorâs performance behavior just like semantic interfaces do for functionality. Since accelerators aimed at improving system performance, their performance behavior should be clearly stated to the users, through a performance interface.
A performance interface intends to abstract away implementation details that do not pertain to performance. A performance interface should be systematically derived that leverage common constructs, such that further tools can be invented to
analyze performance and verify performance properties of the hardware circuit automatically through performance interface.
Background papers
Practical information
- General public
- Free