Saving DVFS: Software Decoupled Access-Execute
Event details
| Date | 20.06.2014 |
| Hour | 10:00 |
| Speaker | Stefanos Kaxiras, Uppsala University, Sweden |
| Location | |
| Category | Conferences - Seminars |
The end of Dennard scaling is expected to shrink the range of DVFS in
future nodes, limiting the energy savings of this technique. This work
evaluates how much we can increase the effectiveness of DVFS by using a
software decoupled access-execute approach. Decoupling the data access
from execution allows us to apply optimal voltage-frequency selection
for each phase and therefore improve energy efficiency over standard
coupled execution.
The underlying insight of our work is that by decoupling access and
execute we can take advantage of the memory-bound nature of the access
phase and the compute-bound nature of the execute phase to optimize
power efficiency, while maintaining good performance. To demonstrate
this we built a task based parallel execution infrastructure consisting
of a runtime system to orchestrate the execution, compiler
infrastructure to automatically concert programs to
Decoupled-Access-Execute, and a modeling infrastructure based on
hardware measurements to simulate zero-latency, per-core DVFS.
Based on real hardware measurements we project that the combination of
decoupled access-execute compiled programs and DVFS has the potential to
improve EDP by 25% without hurting performance. On memory-bound
applications we significantly improve performance due to increased MLP
in the access phase and ILP in the execute phase. Furthermore we
demonstrate that our method can achieve high performance both in
presence or absence of a hardware prefetcher. We are now expanding our
work to target serial programs using a combination of compiler
techniques and hardware features.
future nodes, limiting the energy savings of this technique. This work
evaluates how much we can increase the effectiveness of DVFS by using a
software decoupled access-execute approach. Decoupling the data access
from execution allows us to apply optimal voltage-frequency selection
for each phase and therefore improve energy efficiency over standard
coupled execution.
The underlying insight of our work is that by decoupling access and
execute we can take advantage of the memory-bound nature of the access
phase and the compute-bound nature of the execute phase to optimize
power efficiency, while maintaining good performance. To demonstrate
this we built a task based parallel execution infrastructure consisting
of a runtime system to orchestrate the execution, compiler
infrastructure to automatically concert programs to
Decoupled-Access-Execute, and a modeling infrastructure based on
hardware measurements to simulate zero-latency, per-core DVFS.
Based on real hardware measurements we project that the combination of
decoupled access-execute compiled programs and DVFS has the potential to
improve EDP by 25% without hurting performance. On memory-bound
applications we significantly improve performance due to increased MLP
in the access phase and ILP in the execute phase. Furthermore we
demonstrate that our method can achieve high performance both in
presence or absence of a hardware prefetcher. We are now expanding our
work to target serial programs using a combination of compiler
techniques and hardware features.
Links
Practical information
- General public
- Free
Organizer
- Babak Falsafi
Contact
- Sylvie Thomet