Securing Vulnerable Populations
Event details
| Date | 14.06.2023 |
| Hour | 14:00 › 16:00 |
| Speaker | Boya Wang |
| Location | |
| Category | Conferences - Seminars |
EDIC candidacy exam
Exam president: Prof. Clément Pit-Claudel
Thesis advisor: Prof. Carmela Troncoso
Co-examiner: Prof. Bryan Ford
Abstract
Field Programmable Gate Arrays (FPGAs) witnessed multiple leaps in their programmability through the development of High-Level Synthesis (HLS) tools that enabled more accessibility to non-expert users of FPGAs. The current HLS tools exploit specific types of parallelism in the produced circuits, like Instruction Level Parallelism (ILP). Support of Task-Level Parallelism (TLP) in HLS has been recently explored on FPGAs with systems like ParallelXL, TAPAS, and TaPaSCo. This report examines TLP from a software side through the Cilk runtime system. Second, it analyzes ParallelXL, an effort to bring TLP support to FPGAs using the programming model from Cilk. Then, it investigates a recent graph cycle enumeration algorithm that uses software TLP as a possible candidate for FPGA acceleration. Finally, the report concludes with a research proposal that identifies the line of research to support TLP for FPGAs.
Background papers
Exam president: Prof. Clément Pit-Claudel
Thesis advisor: Prof. Carmela Troncoso
Co-examiner: Prof. Bryan Ford
Abstract
Field Programmable Gate Arrays (FPGAs) witnessed multiple leaps in their programmability through the development of High-Level Synthesis (HLS) tools that enabled more accessibility to non-expert users of FPGAs. The current HLS tools exploit specific types of parallelism in the produced circuits, like Instruction Level Parallelism (ILP). Support of Task-Level Parallelism (TLP) in HLS has been recently explored on FPGAs with systems like ParallelXL, TAPAS, and TaPaSCo. This report examines TLP from a software side through the Cilk runtime system. Second, it analyzes ParallelXL, an effort to bring TLP support to FPGAs using the programming model from Cilk. Then, it investigates a recent graph cycle enumeration algorithm that uses software TLP as a possible candidate for FPGA acceleration. Finally, the report concludes with a research proposal that identifies the line of research to support TLP for FPGAs.
Background papers
Practical information
- General public
- Free